Joªo Guimarªes da Costa

( page 1)

CSM?0 Workshop ? CERN

(July 24, 2000)

MDT Front?End Electronics Integration

MDT Front?End Electronics IntegrationMDT Front?End Electr onics Integration

The "on?chamber" readout elect ronics boards

Testing at Harvard



Test setup



ASD/AMT mezzanine ? CSM link



Noise measurements



Some cosmic rays

Joao Guimaraes da Costa, Greg Novak, Jo hn Oliver

Harvard University

Eric Hazen

Boston University

Jo ª o Guimar ª es da Costa

( page 2)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

The Front ? End Readout ElectronicsThe Front ? End Readout Electronics

Hedgehog boards



3x8 ? Boston Muon Consortium (BMC)



4x6 ? Italy

ASD/ TDC Mezzanine Card



3x8 ? BMC



4x6 ? Italy

Patch Panel



4x6 end ? cap chambers ? BMC



3x8 ? ?

Inverse Patch Panel ? BMC

VME Module & CSM0 ? University of Michigan

DAQ ? U. Michigan

Jo ª o Guimar ª es da Costa

( page 3)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Hedgehog board Hedgehog board

Similar for 4x6 and 3x8

chambers

Long signal traces

Stand ? off will hold ASD

mezzanine card

Jo ª o Guimar ª es da Costa

( page 4)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

ASD ? "lite" Mezzanine Card (rev D)ASD ? "lite" Mezzanine Card (rev D)

Top view

Bottom View

JTAG out(to next card)

JTAG in

(from CSM ? 0)

Data / CTRL

(to/from CSM ? 0)

6 ASD ? "lite" chips

TDC chip

Jo ª o Guimar ª es da Costa

( page 5)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Chamber Service Module Chamber Service Module

VME motherboard CSM ? 0 Mezzanine

Designed at the University of Michigan

RJ45 connectors

Jo ª o Guimar ª es da Costa

( page 6)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Test setup at Harvard Test setup at Harvard

72 tubes

4x6 geometry

Built by the BMC

Prototype of a MDT End ? Cap chamber

Jo ª o Guimar ª es da Costa

( page 7)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Test setup at Harvard Test setup at Harvard

HV side



HV hedgehog boards

from Italy



Based on design from BU

for 3x8 chambers

ASD Mezzanine card

mounted on chamber

prototype

Jo ª o Guimar ª es da Costa

( page 8)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Noise with TDC and CSM0 Noise with TDC and CSM0

CSM0 connected to MDT mezzanin e card

Analog and digital power for

mezzanine board provided by tw o

power supplies

Faraday Cage closed

Digital and analog grounds

connected at Faraday Cage on ly

(jumper on mezzanine board

removed).

Discriminator threshold very

high:~780 mV.

40 Mhz clock seen

Jo ª o Guimar ª es da Costa

( page 9)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Noise Measurements (rev D) Noise Measurements (rev D)

Hit rate at the ASD discriminator

TDC not operating

With added capacitance between

ground and power planes

Bottom/ Top chip asymmetries

Chips on top layer presented higher le vel of noise



Board layer configuration



Top ? signal



Inner 1 ? power



Inner 2 ? ground



Bottom signal

Jo ª o Guimar ª es da Costa

( page 10)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

ASD/ TDC Mezzanine (Rev E) ASD/ TDC Mezzanine (Rev E)

Switched power and ground layers

RJ ? 45 connectors switched to 2 mm ve rtical headers

Digital power added to TDC data cable

Optional shield connection (R ? C to GND) added to all cables

Board is 8 mm narrower to fit w ith patch panel

All connectors moved to center of board to avoid patch panel

Jo ª o Guimar ª es da Costa

( page 11)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

ASD/ TDC Mezzanine card (Rev E )ASD/ TDC Mezzanine card (Rev E)

Jo ª o Guimar ª es da Costa

( page 12)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Problems with Rev E Problems with Rev E

Noise level on bottom chips hi gher than on top chips



Board layer configuration



Top ? signal



Inner 1 ? ground



Inner 2 ? power



Bottom signal



Opposite to Rev D layer configuration (c onfirmed hypothesis)



Solution: add some capacitors

Strips carrying digital power an d ground (on lower part of the card)

couple to ASD inputs



Solution: cut board and run wire instead

Boards are usable after these fi xes

Jo ª o Guimar ª es da Costa

( page 13)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Fixed Rev E board Fixed Rev E board

Top Bottom

Digital gnd & power jumper

Cuts Cuts

Capacitors

Jo ª o Guimar ª es da Costa

( page 14)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Bottom/ Top asymmetry Bottom/ Top asymmetry

With capacitors added between anal og ground and power planes

Re v D board

(no digital)

Jo ª o Guimar ª es da Costa

( page 15)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Noise rate per output channel Noise rate per output channel

Goal: Make all channels at l east as good as top ones

Thres hold specification: 60 mV

Jo ª o Guimar ª es da Costa

( page 16)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Noise rate for several boards Noise rate for several boards

Threshold voltage = 20 mV

Jo ª o Guimar ª es da Costa

( page 17)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

ASD/ TDC Mezzanine (rev F) ASD/ TDC Mezzanine (rev F)

Change from 4 to 6 layers, add an alog ground on bottom

Connect right and left digital se ction with traces in inner layer

Add floating "shield" layers ar ound digital section

Fixed threshold op ? amp (added series resistor)

Moved hedgehog standoff holes 0. 05" to the right

Increased power plane insolation to 0.1"

First 10 boards available this we ek for testing

Final revision for 10k tests ?

Most likely will also be used fo r initial testing of 4x6 chambers

Jo ª o Guimar ª es da Costa

( page 18)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

ASD/ TDC Mezzanine (rev F)ASD/ TDC Mezzanine (rev F)

Layers 2 and 5Layer 3

Layer 4

Layer Analog Digital

1 Signal Signal

2 Ground Floating

3 Power Ground

4 ?????????? Power & signal

5 Ground Floating

6 Signal Signal

Jo ª o Guimar ª es da Costa

( page 19)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

3x8 Mezzanine on 4x6 chamber 3x8 Mezzanine on 4x6 chamber

Remove 3 input resistors

Shift ASD/ TDC card down one p osition

Jo ª o Guimar ª es da Costa

( page 20)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Locking the AMT ? 0Locking the AMT ? 0

Locking the AMT0 can be difficu lty



Need very good grounding



Need low clock ? jitter from CSM0



Low noise environment at the ASD/ TDC Me zzanine card

Jo ª o Guimar ª es da Costa

( page 21)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

CSM0 Clock Jitter Measurements CSM0 Clock Jitter Measurements

1) Time ? interval error

2) Period variation

Measurement of error in each

waveform pulse relative

to a specified reference clock

Measures the period difference

between consecutive cycles in

the waveform

Jo ª o Guimar ª es da Costa

( page 22)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

CSM0 clock output CSM0 clock output

20Mhz component in CSM0

clock of 4 channels

JTAG clock traces in CSM0

close to 40Mhz clock traces

CSM0 Channel 1 CSM0 Channel 4

Jo ª o Guimar ª es da Costa

( page 23)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

CSM0 clock Jitter CSM0 clock Jitter

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

0

20 406080

100120140160180

Jitter 1Jitter 2

CSM channel

Sigma(psec)

Channels with 20 Mhz component

Jo ª o Guimar ª es da Costa

( page 24)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

CSM0 jitter as a function of cable lengthCSM0 jitter as a fun ction of cable length

Jitter increases with cable leng th

AMT ? 0 lock was maintained for cables up to 18 m long

0

1.2

1.7

2.2

2.7

3.3

4.2

5.5

9.8

14.1

15.4

18.4

19.7

24

28 .3

0

50

10 0150200250300

CSM0 clock jitter on ne twork cat.5 cable

Jitter 1Jitter 2

Cable length (m)

sigma (psec)

AMT0 still locks

Jo ª o Guimar ª es da Costa

( page 25)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Jitter on long cables Jitter on long cables

18 m cable

28 m cable

This barely locks

This doesn ‚ t lock

Jo ª o Guimar ª es da Costa

( page 26)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Locking the AMT Locking the AMT

Pulse injected on HV end:



12 mv square pulse injected throu gh 2pF capacitor directely into the

chamber wire (charge = 24 fC)



Same pulse used to trigger CSM0



High discriminator threshold (~200 mV)

Time measurement of leading an d trailing edge of discriminator

pulse

TDC data word

ID TDC# Channel# T E Coarse time Fine time

4?bits 4?bits 5?bits 1 1 12?bits 5?bits

TDC single edge

Jo ª o Guimar ª es da Costa

( page 27)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Fine time measurements Fine time measurements

32 bits of fine time measurement (

lsb = 25ns/32 = 0.78 ns)

Trigger goes from the CSM0 to

AMT0 in next clock edge => it can

be delayed up to 25 ns



Expect fine time measurement to

be flat

Jo ª o Guimar ª es da Costa

( page 28)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Measurement verification Measurement verification

The CSM0 has a pipeline delay of 44 ticks:



The AMT0 trigger offset is set to 4048 (4048 ? 4096 = ? 48)



Search window is 8 ticks and match window is 7 ticks



The CSM uses 3 ticks to send the tri gger to the AMT0. The trigger

arrives at the TDC 47 ticks after the pulse is sent to the ASD through

the cable, attenuator and ASD amplifi er.

The hits have the correct timing for the trigger offset used.

Pulse width measurement

Jo ª o Guimar ª es da Costa

( page 29)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Muon Cosmic Ray Tests Muon Cosmic Ray Tests

Muon tracks

http://www.he pl.harvard.edu/~atlas_electronics

Cosmic ray test using the 72 ? tube chamber prototype



CSM ? 0 triggered by scintillator tele scope



Gas pressure of 3 atm



Voltage = 3.2 kV Threshold = 780 mV

Jo ª o Guimar ª es da Costa

( page 30)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

More pictures More pictures

Showers ?

Jo ª o Guimar ª es da Costa

( page 31)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

More pictures More pictures

Jo ª o Guimar ª es da Costa

( page 32)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Even more cosmics Even more cosmics

Jo ª o Guimar ª es da Costa

( page 33)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Patch Panel Patch Panel

Preliminary design available

Jo ª o Guimar ª es da Costa

( page 34)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Inverse patch panel Inverse patch panel

From CSM ? 0

To Patch Panel on Faraday Cage

JTAG OUT

JTAG IN

Flat ribbon cable

Cat.5 shielded network cable

Bottom layer

Inside aluminum box tied to chamber grou nd

Jo ª o Guimar ª es da Costa

( page 35)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Approaching the final setup Approaching the final setup

2 mezzanine cards

Patch panel & inverse patch panel

Shielded cables

Jo ª o Guimar ª es da Costa

( page 36)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Approaching the final setup Approaching the final setup

Jo ª o Guimar ª es da Costa

( page 37)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Close ? up = > ProblemsClose ? up = > Problems

Tight space next to patch panel = > New position for patch panel?

Thick cables (up to 10 wires plus shields)

Connectors without locks

Huge digital noise feedthroug h due to patch panel

Jo ª o Guimar ª es da Costa

( page 38)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

A 2 Mezzanine card setup that worksA 2 Mezzanine card setup th at works

No patch panel

Cables directly from CSM ? 0

Jo ª o Guimar ª es da Costa

( page 39)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Two ? card test resultsTwo ? card test results

Larger digital noise feedthrough



At the 10% ? 15% level

CSM ? 0 has some problems



Missing word errors



Buffer overflow errors



Lost about 15% of events



Good news: It recovers and keeps going

Jo ª o Guimar ª es da Costa

( page 40)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Cosmic Rays ? 2 ASD Mezzanine cardsCosmic Rays ? 2 ASD Mezzanine cards

Jo ª o Guimar ª es da Costa

( page 41)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Cosmic showers with 2 ASD Mezz anine cardsCosmic showers with 2 ASD Mezzanine cards

Jo ª o Guimar ª es da Costa

( page 42)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Some data Some data

Jo ª o Guimar ª es da Costa

( page 43)

CSM ? 0 Workshop ? CERN

(July 24, 2000)

MDT Front ? End Electronics Integration

Conclusions Conclusions

ASD/ TDC Mezzanine card design is converging



A few cards are available now (rev E)



Thresholds will be about 50% higher than specification



Final 3x8 "lite" ? cards to be ordered in August



Need to use these on 4x6 chambers

Patch panel still under design



Finalize by end of August

ASD/ TDC Mezzanine card ? CSM0 data link works



Need to check problems with 2+ TDCs

More info at



http:\\bmc.bu.edu

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