CSM0 Data Flow/VME

R. Ball

July 24, 2000

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Hardware Structure

n Two physical boards, one VME (6U) format, one

daughter (mezzanine) board

n Logically the hardware is broken into sections,

corresponding to the major components.

n Most hardware components are assigned their own

contiguous subset of VME address space. The

exception to this is the 3 serial/parallel chips

which have no addressing of their own.

n Register content controls the flow of data.

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Hardware Components

n Eighteen independent RJ45 connections to AMT-0

mezzanine cards

n Two RJ45 connections for JTAG, and the

SCANPSC100-F

n VME board based registers

n CSM0 Xilinx (and serial/parallel chips and RAM)

n TTC emulator Xilinx ( TTCem )

n VME FIFO

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RJ45 Jacks

n Eighteen inputs possible, used in any combination

n Bits in CSM register determine active inputs

n JTAG programming determines response of

TDCs .

n Eighteen clocks independent, but will vary in

phase (cable lengths)

n Thirty-five data bits serially x- mitted per word

– Start bit, 32 data bits, parity bit, stop bit

– Bits synchronized with serial clock (+/- 1ns)

– NO DS PROTOCOL AT THIS TIME

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Data Setup

n Program AMT-0 via JTAG

– Run JTAG clock slow enough for all attached cards

n Setup CSM chip registers

– Default register content is ZERO, ie , do nothing

n Enable data flow to begin

– Set flag bits in VME and TTCem registers

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Data Flow

n Valid data words on an RJ45 connection placed in

DS chip output register (one register/channel)

n Data Ready flag raised for that channel

n CSM round-robin polls data ready flags

n Data from channel register stored in DP RAM

n Acknowledge flag for channel raised for one

clock, freeing DS chip channel register

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Data Flow (2)

n DP RAM read follows write by ~6 clocks

n Data ONLY removed from buffer IF it is part of

currently processing event.

n Event data from channel delimited by TDC

header/trailer word pairs.

– EVID and BCID matching are optional in processing

n Data word immediately written to VME FIFO

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Data Flow (3)

n EVID/ WordCount register written with event

information

n “Complete Event Ready” bit is set when valid

EVID/WC value is ready.

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Readout Sequence

n Check if “Complete Event Ready” bit is set

n Read one word from EVID/WC fifo

n Read WC words from VME FIFO

– Read one extra word (a zero) if PDT used instead of

block transfer.

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