ATLAS
July 22, 2000 - J. Wehrley Chapman
MDT Readout Workshop
CERN
July 24-25th
• Goals
- Present ASD/TDC Mezzanine Card
- ASD/TDC Stability/Grounds/Noise
- Present CSM-0 Hardware Design
- Review Hardware Status
- Exhibit Programming Features
- Present WYSIWYG MiniDaq
- Exhibit Software Design
- Discuss Drivers (MiniDaq/UNIX)
- Work with boards (hands on)
- Have Designers Available for ???
Daughter
Card
ATLAS
July 22, 2000 - J. Wehrley Chapman
CSM Workshop Agenda
10:00AM - 12:30 Monday July 24th
Topic Time Speaker
Overview 15 minutes J. Chapman
Goals Discussion 20 minutes J. Chapman - moderator
ASD/TDC Mezzanine Card 45 minutes Joao Guimaraes
Break 20 minutes
CSM-0 Design Overview 20 minutes J. Chapman
CSM-0 Data Flow/VME 20 minutes Robert Ball
Discussion 20 minutes Robert Ball - moderator
ATLAS
July 22, 2000 - J. Wehrley Chapman
14:00 - 15:30 Monday July 24th
Topic Time Speaker
CSM-0 Software Organization 20 minutes Robert Ball
CSM-0 Output Format/Options 30 minutes Robert Ball
Tomographic CSM-0 30 minutes Pietro Binchi
Discussions 30 minutes J. Chapman - moderator
Break 30 minutes
DEMO at Tomograph 120 minutes Robert Ball/Pietro Binchi
ATLAS
July 22, 2000 - J. Wehrley Chapman
Muon Front-end Work
Focus:
ASDs
TDC
MROD
S-Link
S-Link
ROBFE-Link
ASDs
Daisy Chain JTAG
Key Data Rates in Red
CSM
Devices with
internal buffers
CSM-0 functions
shown in Blue
ATLAS
July 22, 2000 - J. Wehrley Chapman
CSM-0 VME Card
Channels 0 - 17
40Mhz Clock Outs
40Mhz Clock In
NIM & ECL Trigger In
JTAG Input
JTAG Output
Daughter Card
Connectors
ATLAS
July 22, 2000 - J. Wehrley Chapman
Workshop CD Contents
• BitString.pdf - document describing the bitstring programming of the AMT-0.1
• BitString.tar.gz - code to perform the bitstring programming of the AMT-0.1
• csm0.001 - file of MiniDaq code used by setup.exe to load the MiniDaq system
• Dataflow.pdf - short LEB99 paper describing the simulations for MDT data flow
• RefGuide.pdf - Reference manual for the MiniDaq system
• setup.exe - Install program for MiniDaq (assumes Nat Inst LabWindows/CVI)
• SimCSM.pdf - Manual describing the CSM design and development (Rev B)
• TomoCSM.pdf - Pietro's transparencies for Workshop
• Tomographic CSM-0.ppt - power point version of Pietro's transparencies
• CSMdesign.pdf - J. Chapman's transparencies for Workshop
• CSMsoft.pdf - Bob Ball's transparencies for Workshop
• verilog - verilog code for the current version of the CSM-0 Xilinx programming
- mux - directory of code for XC4044XLS multiplexing chip
- serial - directory of code for XC4013XLS serial to parallel chip
- ttcem - directory of code for XC4013XLS TTC emulation
- stim - directory of code to emulate events and TDC output
ATLAS
July 22, 2000 - J. Wehrley Chapman
CSM-0 Internal Design
TDC0
TDC5
TDC6
TDC10
TDC17
TDC11
Serial to
Parallel
Xilinx 0
Serial to
Parallel
Xilinx 1
Serial to
Parallel
Xilinx 2
ds_group
32+
32+
32+
1+
1+
1+
18 to 1
Multiplexer
18 DpRAM
based input
FIFOS
VME
FIFO
VME Bus
VME Set
Parameters
32+
DpRAM
mux
32+
32+
ds_group
ds_group
32+
Primary Data Flow Block Diagram
ATLAS
July 22, 2000 - J. Wehrley Chapman
CSM Register Design
• addr 0 -> CSM and TTCem version numbers
- {8'b0, CSM_VERSION, ttcem_version}
• addr 1 -> stop thresholds (read/write)
- {2'b0, stop_bits, 3'b0, stop_threshold}
• addr 2 -> mux disable, TDC hdrs/trls suppress, [17:0] TDC enables (read/write)
- {9'b000000000, enables}
• addr 3 -> csm and tdc header and trailer ids (read/write)
- {5'b00000,DIAG2, DIAG1, DIAG0, ids}
• addr 4 -> evid/word_count fifo output {8'b00000000, data_word}
• addr 5 -> full flags (read only)
- {8'b00000000, stop, in_stop, trig_stop, ext_data_stop, err_sum , fill, fill_bits}
• addr 6 -> header received flags {14'b00000000000000, hdr_rcvd}
• addr 7 -> trailer received flags {14'b00000000000000, trl_rcvd}
ATLAS
July 22, 2000 - J. Wehrley Chapman
CSM-0 Clock and JTAG Block Design
Mezz0
Mezz5
Mezz6
Mezz10
Mezz17
Mezz11
SCANPSC
JTAG
Controller
VME Bus
Mezz0
Mezz5
Mezz6
Mezz10
Mezz17
Mezz11
Clock
Fanout
Serial
Data
Receivers
40Mhz Oscillator
LVDS
Drivers
LVDS
4
4
4
4
4
4
Data to
Serial to
Parallel
Xilinx
Chips
Clock to
Daughter
Card
Rate
Divider