CSM - 1 Calibration Triggers
R.Ball & T.Dai
April 8, 2003
This document is intended to provide a guide on how to work with calibration triggers.
Details of the appropriate TTC command sequence are provided along with screen
captures from the Mini - DAQ and C hipscope logic analyzer traces. The JTAG setup
string for mezzanine boards is not treated.
Calibration Triggers in ATLAS:
Available ATLAS documentation indicates a broadcast B - channel cycle will initiate a
calibration trigger, with the L1accept followi ng at some fixed time after the B - channel
broadcast. In this scenario however, there is no indication as to which of the available
broadcast commands will be used. In fact, there is no discernable indication that a short
broadcast will be used instead of a long cycle.
Further to this, the CSM - 1 has a default duration of 4 m s (160 clock tics) for the
calibration strobe to the mezzanine boards, but for maximum flexibility this must be
programmable. The mechanism we have chosen for this programming is via TTC
Individually Addressed Command (IAC) to the CSM - 1, utilizing both sub - address and
data bits within the long format command frame. If TTC address zero is chosen, then
the command is broadcast to all CSM - 1 at once, allowing them all to be programmed at
once.
The emerging calibration process then becomes maximally flexible if a calibration trigger
can be initiated using either long or short B - channel commands. This is what we have
implemented.
Short Broadcast Commands:
Because we were also testing the capabilities of the TTC/CSM - 1 communications we
chose to use a pair of bits set, one from the user space (bit 6) and one from the system
space (bit 3), as the command indicating that a calibration trigger is being initiated. The
decimal equivalent of this is the value 72 (01001000 binary). When a short format, B -
channel broadcast is received by the CSM - 1 with this value set on the broadcast bit lines,
then a calibration signal of the programmed length is sent to the attached mezzanine
boards in prepa ration for an L1accept calibration trigger. Note that with a delay of zero
duration for the B - channel command, the L1accept will arrive 28 clock tics before the
calibration strobe begins (Figure 1). As the delay then increases, so will the arrival of the
L1accept move later in time with respect to the start of the calibration strobe. A
maximum delay of 255 clock tics can be set.
2
Calibration bit 6 can be synchronized with either de - skewed clock 1 or clock 2,
depending only on the programming of the TTC. If the latter is chosen, then changes to
the fine delay of this second de - skewed clock can scan the calibration across the width of
a single 25ns bucket. See the section below on “TTC Considerations” for warning notes.
Figure 1. Chipscope trace det ailing a calibration trigger initiated from a short - format,
broadcast command. The L1accept is Signal_21, the TTC broadcast strobes 1 and 2 are
Signals_ 15 and 16, respectively, and the calibration strobe is Signal_19.
Long Broadcast (or Individual) Com mands:
The CSM - 1 has been designed to respond to a variety of long - format B - channel
commands. The documentation for the long - format indicates that an Internal/External bit
should be set to indicate if the command is destined internally to the TTC, or ext ernally
to outside electronics. In both cases, the sub - address supplied with the command
indicates exactly what command is to be executed by the addressed components. A TTC
address of zero broadcasts the command to ALL TTCrx devices in the system.
An in ternal sub - address of 4 corresponds to a TTC ERDUMP command. In response the
content of 4 internal TTC registers is clocked out to the TTC external parallel bus pins.
The CSM - 1 monitors for this condition and latches the register content for JTAG
3
readbac k (eg, CSM - 1 Verilog version 0x11). An internal sub - address of 5 corresponds to
a TTC CRDUMP command. The content of another 6 internal TTC registers is then
clocked out as for the ERDUMP command. The CSM - 1 also latches these register
values. The conte nt of the 10 registers is ordered within the CSM JTAG string as shown
in Table 3, page 15, of the TTCrx Reference Manual with lower I2C - addressed registers
in the least significant bit positions. Space for all 20 registers is allocated in the JTAG
string to allow for future I2C readout of the remaining 10. See the TTC documentation
for other internal sub - addresses that are recognized by the TTC but which result in no
externally recognizable actions.
Three external sub - addresses are recognized by the CSM - 1, namely, 1, 2 and 3.
· Sub - address 1: This command causes the CSM - 1 to reset the TTC, reloading its
programming as directed by the CSM - 1 JTAG parameters.
· Sub - address 2: The 8 - bit data value associated with this command is stored and
used as the duration in clock tics of future calibration strobe signals to the
mezzanine boards.
· Sub - address 3: This behaves the same as sub - address 2, except the calibration
strobe is also pulsed in the expectation that a L1accept will follow along just as if
this were a shor t broadcast calibration command.
All other external sub - addresses are ignored.
The timing between the calibration strobe and the L1accept is different when using long
commands instead of short commands in two aspects. First, the B - channel, long - format
co mmand is always synced to de - skewed clock1, so changes in the fine delay will have
no timing - related effect. Second, it takes 26 additional clock tics to send a long
command than it does to send a short command, and so the calibration strobe associated
wi th sub - address 3 will be 26 clock tics later. This means, for example, with a delay of
zero duration for the B - channel command, the L1accept will arrive 54 clock tics before
the calibration strobe begins (Figure 2). And last, but hardly least, the interp retation and
use of the LHC clock by the TTC is not quite the same as that used internally by the
CSM - 1. The TTC documentation is quite specific about when its external signals are,
and are not, valid. However, internally in the CSM - 1 a four - phase core i s used, which
allows the LHC clock division by a factor of four. The primary clock of these four is not
exactly in phase with the TTC clock (although the difference is quite precise) and so it
gives rise to different delays in instances such as the long - f ormat calibration. It may be
wise to re - visit this last issue prior to the fabrication of the final CSM.
4
Figure 2. Chipscope trace detailing a calibration trigger initiated from a long - format,
broadcast command. The L1accept is Signal_21, the cal ibration strobe is Signal_19, and
the initiating “dout” strobe, occurring at time = 60, is Signal_23.
Mini - DAQ Operation for Calibration Triggers
Figures 3 through 6 illustrate the TTCvi command screens and hardware interconnect
during a calibration tr igger sequence. The initial TTCvi control screen (Figure 3) is
selected from the Mini - DAQ “Execute à TTCvi Board Control” menu item. When the
“RUN Type” is switched to “Calibration” from “Normal”, the “Trig. Selection” will
automatically switch to “L1A Cal ib. Trigger”, completing the needed background setups.
Now, the “B - Go/Calib. Control” button in the upper right corner can be clicked, bringing
up the screen shown in Figure 4. B - Go number 2, which is used for calibration triggers,
is now labeled as such . In this figure, it is configured for a short - format calibration. In
Figure 5 it is configured for a long - format calibration, and appropriate values for the
Data/Command (and TTCrx address, sub - address in the case of the long - format) have
been entered i n each case. Click the “FIFO 2” button at the bottom of the screen to
initialize the software, and connect a pulser to the “B - Go 2” lemo input of the TTCvi
(Figure 6) to begin triggering.
5
Figure 3. The TTCvi Control screen as it appears for a calibr ation trigger.
TTC Considerations
The delay between the calibration strobe and the L1accept could change with the final
CSM. This is due to some pin - assignment problems with the current CSM - 1 design, and
the consequent choices made in the Verilog to o vercome the poor placement.
The default TTC programming has its external parallel buses and de - skewed clock 2
disabled to save power. The current CSM - 1 default programming for the TTC has the
parallel buses turned on, but de - skewed clock 2 is not used. These settings will be
established for the TTC each time the CSM - 1 resets it if the “TTC_use_prom” bit is set in
the CSM - 1 JTAG programming.
6
Figure 4. The B - Go control screen set up for a short - format, calibration trigger.
If the TTC control regis ter is modified using a TTC internal IAC, the CSM - 1 has no way
of knowing this. You could, for example, turn on de - skewed clock 2 and select it for
broadcast command synchronization, expecting to do a fine - delay calibration scan. This
would not work thou gh because the CSM - 1 would be unaware of the change and would
still attempt synchronization off clock 1.
Similarly, the registers could be modified to some other temporary purpose incompatible
with a “standard” setup. In this case, an external IAC at sub - address 1 could be used to
reset “standard” TTC operations at the completion of the special purpose task.
7
Figure 5. The B - Go control screen set up for a long - format, calibration trigger.
If the TTCrx is reset from the TTCvi without using the CSM - 1 control, it will reset to its
default parameters. However, the CSM - 1 must present it with a valid TTC address at this
time and won’t know to do so. At the completion of the reset sequence it will therefore
have some random and indeterminate address assig ned.
A watchdog circuit reset will have this same undesirable impact.
8
Figure 6. Front panel of the VME, TTCvi module showing the lemo connection to the
B - Go 2 trigger input (green cable stretching away to the lower left).