November 9, 2001 1
CAST, Inc.
11 Stonewall Court
Woodcliff Lakes
New Jersey 07677 USA
Phone: +1-201-391-8300
Fax: +1-201-391-8694
E-Mail: info@cast-inc.com
URL: www.cast-inc.com
Features
• Available under terms of the SignOnce IP Lic ense
• Optimized for Virtex
TM
, Virtex-E, Virtex-II, and
Spartan
TM
-II
• The I2C Bus Controller performs serial transmission up
to 400kHz and operates in the four following m odes:
- Master Transmitter Mode - Ser ial data output
through SDA while SCL outputs the serial clock
- Master R eceiver Mode - Serial data is received via
SDA while SCL outputs the serial clock
- Slave Receiver Mode - Serial data and the serial
clock are received through SD A and SCL- Slave Transmitter Mode - Serial data is transmittedvia SDA while t he serial clock is input through SCL
Applications
• Embedded microcontroller systems
• Communication systems
AllianceCORE™ Facts
Core Specifics
See Table 1
Provided with Core
Documentation
Core specification,
tests set details
Design File Formats
EDIF Netlist, or
VHDL Source RTL available at
extra cost
Constraints File
i2c.ucf
Verification
VHDL Testbench
Instantiation Templates
VHDL, Verilog
Reference designs &
application notes
Example design
Additional Items
Simulation and synthesis scripts
Simulation Tool Used
1076 Compliant VHDL Simulator
Support
Support provided by CAST, Inc.
Table1:CoreImplementationData
Supported Family Device
Tested Slices
1
Clock
Pads
2
IOBs
2
Performance
(MHz)
Xilinx
Tools
Special
Features
Virtex V50-6 231 1 31 97 M3.1i None
Virtex-E V50E-8 270 1 31 116 M3.1i None
Virtex-II 2V50-5 259 1 31 168 M3.1i None
Spartan-II S100-6 252 1 31 103 M3.1i None
Notes:
1. Optimized for speed
2. Assuming all core I/Os are routed off-chip
I2C Bus Controller
November 9, 2001 Product Specification
I2C Bus Controller
2 November 9, 2001
General Description
The I2C Bus Controller logic provides a serial interface that
meets the Philips I2C bus specification and supports all
t ransfer modes from and to the I2C bus. The I2C logic han-
dles byte transfers autonomously. It also kee ps track of
serial transfers and a st atus register (i2csta) reflects the
s tatus of the I2C Bus Controller and the I2C bus.
TheI2C is amicrocode-freedesigndevelopedfor re usein
ASIC and FPGA implementations. The design is strictly
synchronous wi th positive-edge clocking, no internal tri-
states and a synchronous reset.
Functional Description
The I2C core is partitioned into modules as sh own in Figure
1 and described below.
Arbitration and synchronization logic
In the master mode, the arbitr ation logic checks that every
transm itted logic 1 actually appears as a logic 1 on the I2C
bus. If another device on the bus overrules a logic 1 and
pulls the SDA line low, a rbitration is lost and the I2C imme-
diately changes from master transmitter to slave receiver.
The synchronization logic will synchronize the serial clock
generator with the cloc k pulses on the SCL line from
another device.
Serial clock generator
This programmable clock pulse genera tor provides the
SCL clock pulses wh en the I2C is in the master mode. The
clock generator is switched off when the I2C i s in a slave
mode.
Figure 1: I2C Bus Controller Block Diagra m
November 9, 2001 3
CAST, Inc.
Control logic
The control logic generates the control signal s for serial
byte handling.
Input filter
Input signals are synchronized with the intern al clock (clk),
and spikes shorter th an three oscillator periods are filtered
out.
Address comparator
The comparator compares the received 7-bit sl ave address
with its own slave addres s. It also compares the first
receiv ed 8-bit byte with the general call address (00H). If
equality is found, the appropriate status bits are set and an
interrupt is request ed.
Pin Description
The pinout of the I2C core has not been fixed to specific
FPGA I/O, allowing flexi bility with users’ applications. Sig-
nal names are shown in the block diagram in Fi gure 1, and
in Table 2.
Core Modifications
TheI2C corecanbemodifiedtochangetheserialtrans -
mission bit rate.
Table 2: Core Signal Pinout
Verification Methods
The I2C core’s functionality was verified by means of a pro-
prietary hardware mod eler. The same stimulus was applied
t o a hardware model that contained the original Philips
83C552 chip, and the results compared with the core’s sim-
ulation outputs.
Recommended Design Experience
The user must be familiar with HDL design methodology as
well as instantiation of Xilinx netlists in a hierarchical design
environment.
Ordering Information
This AllianceCORE product is available from X ilinx Alli-
anceCORE partner, CAST, I nc., under terms of the
SignOnce IP License. To learn about the SignOnce IP
License program, contact CAST, Inc., visit www .xilinx.com/
ipcenter/signonce.htm, or write to commonlicense@xil-
inx.co m.
Please contact CAST, Inc., for pr icing and additional infor-
mation ab out this AllianceCORE product.
The I 2C core is licensed from Evatronix SA.
Related Information
80C552/83C552
Single-chip 8-bit microcontroller,
Philips, August 1998.
Xilinx Programmable Logic
For information on Xilinx programmable logic o r develop-
ment system software, cont act your local Xilinx sales office,
or:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: +1 408-559-7778
Fax: +1 408-559-7114
URL: www.xilinx.com
For AllianceCORE-specific information, contac t:
Phone: +1 408-879-5381
E-mail: alliancecore@xilinx.com
URL: www.xilinx.com/products/logicore/alliance /
tblpart.htm
Signal
Signal
Direction
Description
Clock
clkInpu tSystem Clock
Special Function Registers Interface
sfrdatai Input SFR data input bus
sfrdatao Output SFR data output bus
sfraddr InputSFR address bus
sfrweIn putSFR write enable signal
I2C Bus Interface
scliInp utI2C serial clock input
sdaiInp utI2C serial data input
scloOut putI2C serial clock output
sdaoOut putI2C serial data output
Control Signals
scliInp utI2C serial clock input
sdaiInp utI2C serial data input
scloOut putI2C serial clock output