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GOL Reference Manual
Gigabit Optical Link
Transmitter manual
P. Moreira
*
, T. Toifl, A. Kluge, G. Cervelli,
A. Marchioro, and J. Christiansen
CERN - EP/MIC, Geneva Switzerland
May 2002
Version 1.2
*
Technical contact person e-mail: Paulo.Mo reira@cern.ch
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VER SION 1.2 2 PRELIMINARY
Summary of changes ----------------------------------------------------------------------- 5
Chapter 1 ___________________________________________ 6
Introduction ------------------------------------------------------------------------------- ----- 6
System overview ............................................................................... ................................ 6
GOL Architecture ............................................................................... ........................... 6
Modes of operation ............................................................................... ........................ 7
Fast and slow transmission ............................................................................... ..... 8
G-Link mode ............................................................................... ............................ 8
Ethernet mode ............................................................................... ......................... 8
Chapter 2 __________________________________________ 10
Internal Registers ---------------------------------------------------------------------------10
GOL register file ............................................................................... ............................... 10
Register access via the I2C bus and JTAG interface ................................................. 10
Setting parameters via registers or pins ..................................................................... 10
Configuration registers ............................................................................... .................... 11
Config 0 ............................................................................... ........................................ 11
Config 1 ............................................................................... ........................................ 11
Config 2 ............................................................................... ........................................ 12
Config 3 ............................................................................... ........................................ 13
Status Registers ............................................................................... ............................... 1 3
Status 0 ............................................................................... ........................................ 13
Status 1 ............................................................................... ........................................ 13
Chapter 3 __________________________________________ 15
Register Access via the I2C Bus -------------------------------------------------------15
Data and pointer register ............................................................................... ................. 15
Reading and writing registers ............................................................................... ...... 15
Example of a read operation ............................................................................... ........ 15
Chapter 4 __________________________________________ 16
Register Access via the JTAG Bus ----------------------------------------------------16
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JTAG interface Functionality ............................................................................... .......... 16
Scan registers ............................................................................... .............................. 16
Reading and Writing the conf iguration and status registers....................................... 16
Register scan path definition ............................................................................... ........ 17
Chapter 5 __________________________________________ 18
ASIC Operation ------------------------------------------------------------------------------- 18
Data Interface ............................................................................... .................................. .. 18
Initialisation procedure ............................................................................... .................... 18
PLL lock time ............................................................................... ................................ 18
Wait time ............................................................................... ...................................... 1 9
Loss-of-lock count feature ............................................................................... ............ 19
Control of Loss-of-lock behaviour ............................................................................... 19
State definition table ............................................................................... .................... 20
Chapter 6 __________________________________________ 21
Signals and Timing -------------------------------------------------------------------------21
I/o Signal Levels ............................................................................... ............................... 21
ASIC Default Operation Mode ............................................................................... ......... 21
List of signals ............................................................................... ................................. .. 22
Recommended operating conditions ............................................................................ 26
Timing characteristics ............................................................................... ..................... 26
Data interface timing ............................................................................... .................... 27
Transmit latency ............................................................................... ........................... 27
Chapter 7 __________________________________________ 29
Measures against Radiation effects --------------------------------------------------29
Accumulated dose effects ............................................................................... ............... 29
Single Event Upsets (SEU) ............................................................................... .............. 29
Hard-wired configuration data ............................................................................... ...... 29
Hamming-protected configuration register .................................................................. 30
Triple modular redundancy ............................................................................... .......... 30
Up-sized analog components ............................................................................... ...... 31
Chapter 8 __________________________________________ 32
Packaging and Pin Assignments ------------------------------------------------------32
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GOL Package ............................................................................... .................................... 3 2
Pin assignments ............................................................................... ............................... 32
Pin assignments: sorted by signal name .................................................................... 32
Pin assignments: sorted by package pin num ber....................................................... 35
Pin assignments: sorted by ASIC bond pad number.................................................. 38
Package details ............................................................................... ................................. 41
Chapter 9 __________________________________________ 42
JTAG Boundary-Scan ----------------------------------------------------------------------42
JTAG Device ID ............................................................................... ........................... 42
Boundary Scan Register ............................................................................... .............. 42
Boundary scan register read out order ................................................................. 42
Appendix A ________________________________________ 44
Timing and Currents Tables -------------------------------------------------------------44
Wait time encoding table ............................................................................... .............. 44
PLL_lock_time encoding table ............................................................................... ..... 45
Loss_of_lock_time encoding table .............................................................................. 45
Charge-pump current encoding table ......................................................................... 46
Laser-diode bias current ............................................................................... .............. 46
Line-driver strength selection ............................................................................... ....... 46
Appendix B ________________________________________ 48
Configuration and Status register summary ---------------------------------------48
References ------------------------------------------------------------------------------- ------50
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VER SION 1.2 5 PRELIMINARY
Summary of changes
Version 1.2
? Several typographical errors correct ed.
Version 1.1
Package information added to the m anual.
Version 1.0
Laser driver problem identified and corrected.
I/O: TTL and 5V CMOS tolerant.
LVDS / PECL differential clock input added.
Open fiber control safety logic ad ded.
? Schmitt trigger cells added for the I2C signals.
I2C pointer register is now Read / W rite.
JTAG ID updated.
ESD protection improved.
Pinout redefined.
Version 0.1
Pin names corrected for bond-pads number 13 to 16. Please see pin assignments
table on page 32.
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VER SION 1.2 6 PRELIMINARY
Chapter 1
Introduction
Gbit/s data transmission links w ill be used in the in trigger and data acquisition
systems of several LHC detectors. In thes e applications, the transmitters, located
inside the detectors, will be subject to hi gh radiation doses.
The Gi gabit Optical Link (GOL) chip, is a multi-protocol high-speed transmitter ASI C,
which is able to withstand high doses of radiation. The IC supports two standard
protocols, the G-Link and the Gbit-Etherne t, and sustains transmission of data at both
800 Mbit/s and 1.6 Gbit/s. The ASIC was im plemented in a 0.25 µ m CMOS
technology employing radiation tolerant lay out practices.
SYSTEM OVERVIEW
In the four LHC experiments (ATL AS, CMS, ALICE and LHCb), high-speed (Gbit/s)
data links will be used in the trigger and data acquisition systems. In these links, the
flow of information will be unidirectiona l, that is, the transmitters will be located inside
the detectors and the receivers will be sit uated in the experiment‚s counting rooms. A
consequence of this arrangement is that the transmitters will be subjected to high
levels of radiation while the receivers wi ll operate in a radiation free environment.
In this manual, the Gigabit Optical Link (G OL) transmitter ASIC, that has been
designed to operate reliably under the radi ation conditions encountered inside the
LHC detectors, is described. Since the rece ivers do not require any type of radiation
hardness, commercial devices will be us ed together with GOL IC‚s to assemble
complete data links.
Operating the transmitter ASIC in a link wi th a standard commercial receiver imposes
some compatibility constraints: Namely, data formats, data rates and coding schemes
have to be respected. Additionally, for tr igger links the constant latency requirement
imposes data rates that are multiples of the LHC master clock frequency. In most
applications, the detector systems require the transmission of either 16 or 32 bits of
data in a single LHC clock cycle. The ASIC was designed to support both the 8B/10B
[1] and the CIMT [2] line coding schemes . Both schemes introduce an overhead of
two additional bits for each eight bits of data. Therefore, the required data rates are
either 800 Mbit/s or 1.6 Gbit/s for 16 or 32-bit data transmission. These result in
effective data bandwidths of 640 Mbit/s a nd 1.28 Gbit/s, respectively.
GOL Ar chitecture
The block diagram of the ASIC is shown in Figure 1. Its operation can be described
as follows. At every master clock cycle (LH C clock), data is presented to the
transmitter inputs either as a 16 or 32-b it word. When the 32-bit mode is selected the
input data is time division multiplexed in two 16-bit words that are sequentially
processed by the line-code encoders. If 16- bit mode is selected, only a single word is
processed in a 40.08 MHz master clock cycle . Which line-coding scheme is used is
the choice of the user. If the ÍConditional -Invert Master TransitionÎ (CIMT) [2]
encoding scheme is employed, a G-Link rece iver is required while if, 8B/10B [1]
coding is performed then either Gbit Ethern et or Fibre Channel receivers can be
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used, provided that they are compatible wit h the data rate being generated. While
CIMT encoding is done in a group of 16-bits at a time, 8B/10B encoding is specified
for 8-bit words. To avoid treating the tw o coding schemes differently, the 8B/10B
encoder was designed to process two 8-bit w ords in parallel. Before being fed to the
serializer, the 20-bit encoded words are ti me division multiplexed in two 10-bit words
by the word-multiplexer. The 10-bit high-s peed serializer converts its input into a
serial stream of either 800 Mbit/s or 1.6 G bit/s. The serial data is then fed to the laser-
driver and to the 50 ? line-driver. These can be used ei ther to intensity modulate a
lase r or to drive a 50 ? transmission line with Pseudo ECL levels. Due to radiation
effects, it is expected that the threshold current of the laser diodes will increase with
time over the lifetime of the experiments [3]. To compensate for this, the laser-driver
contains an internal pre-bias current gener ator that can be programmed to sink
currents between 0 and 55 mA. Programmi ng the ASIC can be done using either an
I2C [4] or a JTAG [5] interface. External hardwired pins set the main operation modes
of the receiver.
I2C
JTAG
D(31:0)
16/32b
CIMT
Encoder
8B/10B
Enc oder
16b
Serializer
Data
Interface
Control &
St atus
Registers
20b
50 ?
Line
Driver
Laser
Driver
out+
out-
PLL &
Clock
Generator
LHC clock
Word
Multiplexer
10b
Figure 1 GOL block diagram.
Modes of operation
Mode line
coding
scheme
conf_
wmode16
pin
conf_
glink
pin
Input
bus
width
Internal
clock
speed
[MHz]
data
rate
[Mbit/s]
net data
rate
[Mbit/s]
Ethernet
fas t
8B/10B 0 0 32 80 1600 1280
G-LINK
fast
CIMT 0 1 32 80 1600 1280
Ethernet
sl ow
8B/10B 1 0 16 40 800 640
G-LINK
slow
CIMT 1 1 16 40 800 640
Table 1 The four basic modes of operation
The Gigabit Optical Link (GOL) transmitter circ uit supports a total of 2 x 2 different
modes of operation: G-Link and Ethernet mode, both either fast ( 1.6 Gbit/s ) or slow
( 0.8 Gbit/s ). These modes, which are summaris ed in Table 1, are selected by wiring
the pins conf_glink and conf_wmode16 to the required logic value. A lo gic Í1Î on
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conf_glink selects G-Link mode. Otherwise , the chip operates in Ethernet mode. A
logic Í1Î on conf_wmode16 selects the slow transmission m ode, using only the 16
least sign ificant bits of the input data bus ( din<15:0>) . A logic Í0Î chooses fast
transmission mode, using 32-bit data, ( din<31:0> ). In both G-Link and Ethernet mode,
the line coding adds 2 bits for each 8 bits of data, such that the effective data rate is
80 % of the transmission bandwidth. The enc oding takes care that the transmitted
sequence is DC free, and the run-length of zeros or ones is limited.
Fast and slow transmission
In the fast transmission mode, which is selected when conf_wmode16 is zero, 32 bits
of data are transmitted during a 40 MHz cl ock cycle, resulting in 1.6 Gbit/s data rate.
In the slow transmission mode, only 16 bits of data are transmitted, resulting in a final
data rate of 800 Mbit/s. Throughout this m anual, the denominations " fast " and " 32-bit "
mode, and " slow " and " 16-bit " mode will be used sy nonymously.
G-Link mode
When the chip is configured to be in G-Link mode, the ÍConditional-Invert Master
TransitionÎ (CIMT) [2] transmission form at is used. The chip reads the data to be
transmitted from the input bus din<31:0> . The pins cav , dav and FF, are used to
control the transmission. An additional "f lag" data bit can be added to each 16-bit
word via the flag<1:0> signals. flag<1> is transmitted together with the upper 16 bits
(corresponding to din<31:16> ), and flag<0> to the lower sixteen bits ( din<15:0> ). In
the 16-bit mode, only bits din<15:0> and flag<0> are used.
If the chip is in the ÍREADYÎ state, the va lue on din<31:0> is transmitted as either a
data or a control word, depending on wh ether the dav or the cav signal is activated. In
the case that neither cav nor dav is Í1Î, the idle pattern is transmitted. If FF is Í0Î,
then the special symbol ff0 is sent, which allows the receiver to gain synchronisation
(see T able 2). In the 32-bit mode, data is transmitted with the lower bits firs t, i.e. the
data word din<15:0> is serialised before din<31:16> . When transmitting a control
frame, only bits din<29:16> and d in<13:0> are used (two 14-bit control words). In the
16-bit mode, only bits din<13:0> are used ( one 14-bit control word).
cav dav FF G-Link Frame
0 0 0 IDLE (ff0)
0 0 1 IDLE (ff1)
0 1 X DATA, din<31:0>
1 0 X COMMAND frame
1 1 X COMMAND frame
Table 2 G-Link transmission modes
Ethernet mode
In Ethernet mode, each byte is converted in to a 10-bit word for transmission using the
8B/10B-encoding standard [1]. The transmiss ion order is defined as going from the
lower to the upper bits. Thus, din<7:0> is transmitted before din<15:8> etc. In
Ethernet mode, two signals control the tran smission: tx_en , and tx_er . These pins are
shared with dav and cav used for G-Link mode. If the chip is in the ÍREADYÎ state,
the sym bols will be transmitted according to Table 3. When tx_en is asserted and
tx_er is not asserted then the data bits from pins din<31:0> are encoded and
transmitted normally. When tx_en is not asserted and tx_er is asserted, then the
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encoder will generate a carrier ex tend [1] consisting of four (or two
1
)
If tx_en and tx_er are both asserted then the transm it error propagation code
(
the IDLE sequence (
tx_er tx_en Encoded 10 bit output
0 0 IDLE (
0 1 Normal data (from din <15:0> or di n<31:0>)
1 0 Carrier extend (
1 1 Transmit error propagation (
Table 3 Ethernet transmission modes.
1
Depending on the transmission mode: F our bytes in fast (32-bit), 2 bytes in slow (16-bit) mode.
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Chapter 2
In ternal Registers
In this Chapter , the internal registers of the gigabit optical link, accessible via the I2C
and the JTAG interface, are descr ibed in detail. A brief summary of this chapter can
be found in Appendix B.
GOL REGISTER FILE
The GOL chip contains six user-accessible r egisters, which are listed in Table 4. The
register file is divided into four configur ation registers and two status registers. While
configuration registers can be both read and written, status registers can only be
read. The configuration registers are inter nally protected with Hamming check bits. If
one bit flips due to a single event upset ( SEU), it is automatically corrected (see also
Chapter 7, "Measures against radiation effe cts").
I2C reg.
address
Register name
Default content
(after reset)
Configuration registers
0 Config 0 00110011 ($33)
1 Config 1 00011111 ($1F)
2 Config 2 00010000 ($10)
3 Config 3 00100000 ($20)
Status registers
4 Status 0 00000000 ($00)
5 Status 1 -
Table 4. The GOL register file.
Register access via the I2C bus and JTAG interface
All four configur ation registers can be read and written via both the I2C and the JTAG
interface. The two status registers allo w only read access. How to use the I2C and
the JTAG interfaces to access these regist ers is described in Chapter 3 and Chapter
4, respectively.
Setting parameters via registers or pins
Some parameters, i.e. the PLL c harge pump current, the laser driver current and the
line driver strength, can be set either by hard-wiring pins (e.g. conf_i_pll ) or by using
the values stored in the configuration re gister. Bit 7 of Config register 3
("us e_conf_reg s") determines where the settings s hould be read from the pins ("0") or
the registers ("1"). The "pinÎ setting is intended for a usage of the GOL where register
access with either the I2C or JTAG bus is not possible. The default value of
use_conf_regs is "0", thus after a reset the se ttings from the pins are used. Since the
number of pins was limited, the hard-wir ed settings only decode a subset of the
register settings. Table 20, 18, and 19 (p age 46) define the pin encoding, and their
corresponding register settings.
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CONFIGURATION REGISTERS
Config 0
Bits Name Description
<4:0> Wa it_time Defines the time to wait between the
ÍLOCKEDÎ state and ÍREADYÎ state
<7:5> Loss_of_lock_time Defines the number of er roneous
cycles the chip tolerates befo re it
goes into the ÍOUT-OF-LOCKÎ state
Table 5 Bit assignment of Config regist er 0.
Wait_time :
after start-up and after the transmitter ASIC is properly synchronised,
some time (Íwait timeÎ) must be allowed for the link receiver
to synchronise with the
incoming data stream. During this period, idle c haracters are transmitted. The wait
time bits ( Config0<4:0> ) allow to control the duration of the wait time (see Table 17,
page 44).
Loss_of_lock_time : Since the ASIC will be operatin g in a radiation environment, it is
possible that Single Event Upsets (SEU) wil l momentarily disturb the internal PLL
operation. Internal to the IC, a watchdog c ircuit monitors the correct operation of the
PLL circuit and reinitialises the ASIC oper ation in the case gross synchronisation
errors have occurred. It is however possibl e that, after an SEU, the ASIC (and the link
receiver) can resume normal operation wit hout the intervention of this watchdog
circuit. The Loss_of_lock_time bits ( Config0<7:5> ) allow to control the amount of tim e
the error condition must persis t before the watchdog circuit will reinitialise the IC (see
Table 19, page 45).
Config 1
Bits Name Description
<3:0> PLL_lock_time Defines the time bet ween the OUT-OF-
LOCK state and t he LOCKED state.
<4> en_soft_loss_of _lock If 1 then the GOL can tolerate a number
of erroneous cycles defined by
Loss_of_lock time, otherwise the state
goes immediately to OUT-OF-LOCK
after the first error.
<5> en_loss_of_lock_count If 1 then one TX_LO LC cycle is inserted
between LOCKED a nd READY, where
the number of loss-of-l ock events is
transmitted as a 16-bit da ta word.
<6> en_force_lock [Disables l ock state machine if 1. Only
used for testing/debugging.]
<7> en_self_test If 1, a running 16 bit counter generates
transmission data
Table 6 Bit assignment of Config register 1.
PLL_lock_time : After power up (or after a synchr onisation loss due to an SEU), the
lock acquisition state machine requires the PLL lock signal to be stable for a given
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amount of time before it considers the PL L to have acquired lock. This elapsed time is
controlled by bits Config1<3:0> (see Table 18, page 45).
En_soft_loss_of_lock : If the feature Í soft loss of lock Î is disabled ( Config1<4> = Í0Î)
then, whenever a synchronisation loss is detected, a re-initialisation cycle is
immediately started. However, if the Í soft loss of lock Î feature is enabled ( Config1<4>
= Í1Î) then a re-initialisation cycle is only started if a number of erroneous cycles,
defined by the Í Loss_of_lock_time Î, has occurred (see " Config 0 ", Table 5 and Table
19 (page 45)).
En_loss_of_lock_count : the ASIC keeps track of how many s ynchronisation losses
have occurr ed since the last reset. If the bit en_loss_of_lock_count is set to Í1Î
(Conf ig1<5> =Î1Î), a special word is transmi tted by the ASIC with the Í loss of lock
count Î information at the time the chips enters the "READY" state. If the ASIC is
operating in the G-Link mode, the Í loss_of_lock_count Î is transmitted as a control
word. If the Gbit Ethernet mode is selected, the Í loss_of_lock_count Î is transmitted as
an ordinary data word.
En_force_lock : If enabled ( Config1<6> ="1") the IC operates as if the PLL was
always locked. This mode is available for testing purposes only.
En_self_test : when this mode is enabled ( Config1<8> = Í1Î), the ASIC ignores the
data on din<31:0> , and generates an internal data s equence. This sequence consists
of a cyclic 16-bit count. The transmitted sequence is identical for slow (16 bit) and fast
(32 bit) mode: n< 7:0>, n<15:8>, n+1<7:0>, n+1<15:8>, n+2<7:0>...
Config 2
Bits Name Description
<4:0> PLL_current Defines the charge-pump current of the
internal phase-locked loop (PLL).
<6:5> test_sel [Selects signal to appear on test_analog
pad. Only used for testin g/debugging.]
<7> en_flag Enables fl ag bits in G-Link mode
Table 7. Bit assi gnment of Config register 2.
PLL_curr ent : The PLL charge pump current is set at start-up by reading the
hardwired ASIC input signal Í conf_i_pll Î according to Table 20, page 46. T he charge
pump current can also b e programmed by writing into bits Config2<4:0> . For this to
have an effect bit Config3<7> has to be set to Í1Î. In this case , the charge-pump
current is giv en by:
I
charge-pump
= Config2<4:0> × 1.25 µ A
En_flag : when transmitting data in the G- Link mode, a flag bit is always added to
each 16 bits of data being transmitted. W hen the external flag bits are disabled
( Config2<7 > = Í0Î), the flag bit data is gener ated internally in the ASIC and alternates
between Í0Î and Í1Î for every 16-bit word transmitted. If the external flag bits are
enabled, then the value of the flag<1:0> pins is used. When operating in the 32-bit
mode, flag<1> is transmitted together with the up per 16 bits (corresponding to
din<31: 16> ), and flag<0> with the lower 16 bits ( din<15:0> ). In 16-bit mode, only
flag<0> is used.
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Config 3
Bits Name Description
<6:0 > LD_current /
driver_strength
Defines the bias current for the Laser
Driver (LD) or the streng th of the 50
Ohm line driver
<7> use_conf_regs When 1, the conten t of the Configuration
registers 1 and 2 are used to define the
value for PLL_c urrent and LD_current. If
0, the values are derived from the
encoded values on the pads.
Table 8. Bit assignment of Config register 3.
LD_current : In laser driver mode ( conf_laser ="1"), and provided that
"us e_conf_regs " = "1", these bits ( Config3<6:0> ) allow programming the laser-diode
bias current. The number in bits Config3<6:0> translates the laser-diode bias curr ent
according to:
I
ld-bias
= 1 mA + Config3<6:0> × 0.4 mA
If " use_conf_regs " = "0" then the bias current is set according to the value hardwired
on pins conf_i_ld<1:0> (see Table 21, page 46).
driver_strength : In the 50 ? line driver mode ( conf_laser ="0"), and provided that
"us e_conf_regs " = "1", Config3<6:0> contains the strength of the line driver, as
defined in T able 22, page 47.
Use_conf_regs : When set ( Config3<7> = ‘1’ ) bits Config3<6:0> are used to set the
laser-diode bias current and bits Config2<4:0> are used to set the PLL charge pump
current. If this feature is dis abled ( Config3<7> = ‘0’ ) then the pins Í conf_i_ld<1:0> Î
and Í conf_i_pll Î are used to set these currents.
STATUS REGISTERS
Status 0
Bits Name Description
<7:0> loss_of_lock_count Number of "loss-of-lock" events since
last reset.
Table 9. Bit assignment of Status register 0.
Loss_of_lock_count : This register accumulates the num ber of times the PLL has
been det ected to be out of lock since the last ÍRESETÎ. This value can be read from
the I2C interface or, if the Í En_loss_of_lock_count Î feature is enabled (see
configuration-register ÍConfig 1Î), this c ount will be transmitted each time lock has
been regained.
Status 1
Bits Name Description
<7:6> link_control_state_A Current stat e of link initialisation logic A
<5:4> link_control_state_B Current state of link initialisation logic B
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<3:2> link_control_state_C Current stat e of link initialisation logic C
<1> c onf_glink Reads value on conf_glink pin. If 1, then
the chip is configured on G-Link mode,
otherwise in Ethernet mode.
<0> conf_wmode16 Reads value on conf_wmode16 pi n. If 1
then the chip accepts 16-bit wid e data
and transmits with 800 Mbit/s , otherwise
32 bit data and 1.6 Gbit/s s peed.
Table 10 Bit assignment of Status register 1.
Link_control_state_A, li nk_control_state_B, and link_control_state_C : For SEU
robustness, the ASIC state machines use tr iple modular redundancy and majority
voting. Bits Status1<7:6> , Status1<5:4> and Status1<3:2> can be read through the
I2C or JTAG interface, and they represent t he state of link initialisation logic. The
meaning of these bits is as follows (see ÍI nitialisation procedureÎ, on page 18).
00 : ÍOUT-OF-LOCKÎ state
01 : ÍLOCKEDÎ state
10 : ÍREADYÎ state
11 : ÍTX_LOLCÎ state
Conf_glink : reports the hardwired value of pi n Í conf_glink Î
Conf_wmode16 : reports the hardwired value of pi n Í conf_wmode16 Î
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VER SION 1.2 15 PRELIMINARY
Chapter 3
Register Access via the I2C Bus
T he I2C bus protocol defines a standard for an asynchronous serial bus with a
maximum transfer rate of one Mb it/s [4].
DATA AND POINTER REGISTER
All data transfer over the I2C bus is performed using only two registers: The
I2C_pointer-register and the I2C_data-register . The I2C_pointer-register is 3 bits
wide and contains the address of the intern al register as defined in Table 4, page 10.
When reading the I2C_data-register , the content of the register being addressed by
the pointer r egister is transferred. Conversely, writing a byte to the I2C_data-register
in fact writes to the GOL register addressed by the I2C_pointer-register .
Reading and writing registers
All the registers shown in Table 4 can be accessed over the I2C bus. After a write
access, the corresponding configuration reg ister is in general set to the value of the
transmitted data byte. A write access to o ne of the status registers will be ignored.
Each I2C access is performed in two steps:
1) Write the register number in the I2C_pointer-register
2) Read or write the I2C_data-register
In accordance with the I2C bus specificati on, each device on the bus is addressed by
a 7-bit wide I2C device address. Each GOL c hip occupies two consecutive positions
in the 7-bit I2C address space. Hence, it is possible to address a total of 64 devices in
one system. The 7 Bit I2C address is derive d from the content of the value on the
i2c_addr<6:1> pins in the following way:
I2C access
register name
resulting 7 bit
I2C address
I2C_pointer {i2c_addr<6:1> , 0 }
I2C_data {i2c_addr<6:1> , 1 }
Table 11 I2C address calculation.
Example of a read operation
Assuming, that we intend to read the conten t of the Status 0 register, and the
i2c_addr<6:1> pins are hard-wired to "110001". T he procedure is as follows:
Firs t, by writing the value 4 (=register number according to Table 4, page 10) on I2C
address 1100010, the pointer register is set. This is then followed by a read access
onto the I2C address 1100011 (the data re gister), which delivers the content of the
Status 0 register.
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Chapter 4
Register Access via the JTAG Bus
The JTAG standard defines a serial communication protocol for testing and
programming purposes.
JTAG INTERFACE FUNCTIONALITY
In the GOL chip, the JTAG interface sup ports three tasks
• Boundary scan
• Acces s to internal configuration and status registers
• Test of internal logic
The differ ent functions are reflected in a number of scan registers, which are list ed in Table
12. A specific sc an path can be selected by writing its 5-bit code into the instruction regist er
(IR) inside the on-chip JTAG c ontroller [5]. Table 12 lists all available scan registers: The
EXTEST register is used for boundary sc an testing, which is described in Detail in Chapter 9,
"JTAG boundary scan". The DEVICE_ID regist er can be used to read the JTAG identification
number. The CONF_RW and CONF_R registers ar e used to transfer data from (and to) the
configuration and status registers. The COR ETEST register provides a simple means of
verifying the correct function of the inter nal logic for production testing. The BYPASS register
is used to short-circuit the scan-path if , for example, JTAG testing is used with more devices
in a system.
Scan registers
JTAG scan register JTAG
Instr. reg.
content
Length of scan
path
EXTEST 00000 57
DEVICE_ID ("$14535049") 00001 32
CONF_RW 01001 55
CONF_R 01010 55
CORETEST 01011 432
BYPASS 11111 1
Table 12. The available JTAG registers in the GOL chip together with the required
instru ction register code.
Reading and Writ ing the configuration and status registers
Two scan registers are defined for accessi ng the configuration and status registers,
CONF_RW and CONF_R. While the first one is for read and write access, the latter
only reads the data from the configurat ion and status registers. The only difference in
the implementation of these two is that in the case of CONF_R the update cycle
("Update-DR", see [5]) does not lead to a c hange in the configuration registers. Using
the CONF_RW scan path, the current register content is shifted out at the same time
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that a new register content is shifted in the scan path. During the Update-DR cycle,
the configuration registers are then loa ded with the new values.
Register scan path definition
The shifting order for the CONF_RW and CONF _R scan paths is defined in Table 13.
Besides the two status registers and the f our configuration registers, the scan path
contains a seven bit hamming check-sum of the 32 bits configuration data. For write
access, only the values of the configuratio n registers are significant, values written to
the status registers or the hamming check-s um are ignored.
Position
shift OUT
Position
shift IN
Signal/Register content
0 54 status 0<0>
1 53 status 0<1>
... ... ...
7 47 status 0<7>
8 46 status 1<0>
... ... ...
15 39 status 1<7>
16 38 config 0<0>
... ... ...
23 31 config 0<7>
24 30 config 1<0>
... ... ...
31 23 config 1<7>
32 22 config 2<0>
... ... ...
39 15 config 2<7>
40 14 config 3<0>
... .... ...
47 7 config 3<7>
48 6 hamming<0>
... ... ...
54 0 hamming<6>
Table 13. Scan path definition for register access using the CONF_RW and CONF_R
modes.
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Chapter 5
AS IC Operation
During normal operat ion, the GOL chip reads a 32 (or 16 bit) word from the din<31:0>
bus, and puts out its corresponding serial bit stream on either the laser or the 50 ?
line driver. An internal phase-lock ed loop (PLL) generates the high-speed clocks from
the external clock source, which is the 40.08 MHz LHC clock. The transmission is
therefore completely synchronous with fix ed latency. If the PLL is not properly locked
to the clock signal, then the data values on din<31:0> are ignored, and a proper idle
symbol is transmitted. An initia lisation procedure is performed, which is described
below
DATA INTERFACE
The data interface samples the following in put signals
• din<31:0>
• flag<1:0 >
• dav / tx_en
• cav / tx_ er
• FF.
If in 32 bit mode, the data interface also converts 32 bit wide data into 16 bit words,
which are then fed to either the G-Link or the 8B/10B encoder. The signals have to
fulfil timing (setup and hold time) require ments with respect to either the rising or the
falling edge of clkLHC (See Chapter 6, "Signals and Timi ng", Figure 4 and Figure 5).
The conf_negedge pin specifies if the positive or ne gative edge of clkLHC is to be
used to sample the input signals.
INITIALISATION PROCEDURE
A state machine controls the lock acquisiti on behaviour of the circuit. Its state diagram
is depicted in Figure 2, and the differ ent states are listed in Table 14. After a reset or
after the ASIC’s internal PLL has lost lock , the lock monitoring state machine enters
the ÍOUT-OF-LOCKÎ state.
PLL lock time
Having entered the "OUT-OF-LOCK" state, t he state machine waits until it is certain
that the phase-locked loop has acquired ph ase lock with the reference clock. This is
done by counting ÍmÎ consecutive cycles in which the PLL asserts the Íinstant_lockÎ
internal flag. (The "instant_lock" signal originates in the analogue circuitry of the PLL.
Although a "1" on this signal is not necess arily an indicator of a properly locked PLL,
a "0" is a certain indicator that the P LL is not
locked.) The count ÍmÎ is def ined by the
bits Í PLL_lock_time Î (see "Config 1", page 11 and T able 18, page 45). After "m"
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cycles, the state machine enters the "LOCKE D" state. During the "OUT-OF-LOCK"
and ÍLOCKEDÎ states, an ÍIDLEÎ symbol
2
is transmitted.
Wait time
The chip stays in the "LOCKED" state for a period of time long enough to assure that
the receiver can acquire phase lock with t he incoming bit stream.
LOCKED
READYTX_LOLC OUT-OF-LOCK
instant_lock = 1 during m consecutive cy cles,
m defined by PLL_lock _time
instant_lock = 1 durin g n consecutive cycles,
n defined by PLL_wait_time
en_loss_of_lock_count=0
inst ant_lock = 1 during n consecutive cycles,
n defined by PLL_wait_time
en_loss_of_lock_count = 1
(instant_lock = 0) and (en_soft_lockloss = 0) or
(instant_lock = 0 during k cycles
k defined by loss_of_lock_time
00 01 10 11
Reset
Figure 2 Lock acquisition and monitoring st ate diagram
The duration of this period, "n" cycles, is controlled by the Wait-time. The wait time is
derived from the value in Config 0, as def ined in Table 17 (page 44). After this time
has elapsed (and provided that the "insta nt_lock" signal remains "1") the transmitter
enters the "READYÎ state were transmissi on of data is resumed.
Loss-of-l ock count feature
The "READY " state is entered directly from the ÍLOCKEDÎ state if the Í Transmit Loss
of Lock Count Î feature is disabled, that is, en_loss_of_lock_count = Í0Î (see Config 1
(page 11)). If, however, this feature is en abled ( en_loss_of_lock_count = Í1Î) then,
before entering the ÍREADYÎ state, an inter mediary ÍTX_LOLCÎ cycle is inserted. In
this state, the number of times a loss of s ynchronisation has been detected since the
last ÍRESETÎ is transmitted over the link ( see Config 1). In G-Link mode this is a 16
bit control word, in Ethernet mode the loss -of-lock counter is transmitted as an
ordinary data word.
Control of Loss-of-lock behaviour
The ASIC has been designed to operate in a radiation environment, where Single
Event Upsets (SEU) will eventually distur b the internal PLL operation. To decide if the
PLL is operating properly the Í instant_lock Î signal is constantly monitored. Du ring
normal operation this signal should have the logical value Í1Î. However, when phase
lock is lost this signal takes the logic va lue Í0Î. The user has the choice between a
hard ( en_soft_loss_of_lock = Í0Î) or a soft ( en_soft_loss_of_lock = Í1Î) detection of
synchronisation loss (see Config 1, pa ge 11). If the hard decision is used and
instant_lock = Í0Î for a single cycle, the lock monitoring state machine enters the
ÍOUT-OF-LOCKÎ state. If the soft decision mode is selected, the lock monitor state
machine has to det ect that the signal instant_lock is Í0Î for "k" cycles (consecutiv e or
not) before it goes into th e "OUT-OF-LOCK" state. This count is reset to zero if 1024
2
The actual value of the idle sequence depe nds on the operation mode (G-Link or Ethernet).
10
11
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VER SION 1.2 20 PRELIMINARY
consecutive cycles with instant_lock = Í1Î are detected before the count reaches the
value ÍkÎ. The number "kÎ corresponds to the " loss_of_lock_time " in configuration
register 0 (see page 11). The mapping between the value of loss_of_lock_time and k
is defined in Table 19 on page 45.
State definition table
State link
control
state
Description transmitted symbol ready
pin
OUT-OF-LOCK 00 PLL is unlocked IDLE 0
LOCKED 01 PLL has acquired
lock
IDLE 0
TX_LOLC 11 Transmit content of
loss_of_lock_counter
loss_of_lock_count 0
READY 10 Normal operation Data from the data
bus
1
Table 14 Table of states of the lock acquisition state machines.
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Chapter 6
Signals and Timing
This chapter describes the GOL signal pins and the most important timing relations
among these signals.
I/O SIGNAL LEVELS
With the exception of the high-speed seri al outputs and the differential clock inputs,
all the I/O signals can be interfaced wi th 2.5V and 3.3V CMOS circuits as well as with
TTL logic (5V tolerant).
ASIC DEFAULT OPERATION MODE
The ASIC basic operation modes are set by a series of signal pins. These should be
hardwired according to the data rate, trans mission protocol and use with a laser-
diode or a 50 ? transmission line. However, the c onfiguration pins include either pull-
up or pull-down resistors. This allows to o perate the chip in its default mode without
hardwiring these pins. The default operati on mode is:
? G-Link mode;
16-bit data bus;
Laser driver operation;
Data bus sampled at the rising edg e of the reference clock;
Differential reference clock inpu t active;
PLL charge-pump current: 10 µ A;
µ Laser bias current: 5.8 mA;
I2C address: 0;
I2C signal SCL pulled up;
JTAG signal JTAGCLK pulled up;
JTAG signal JTAGTDI pulled up;
JTAG signal JTAGTMS pulled up;
JTAG signal JTAGTRST_b pulled down;
Test signal test_shift pulled down.
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LIST OF SIGNALS
The various signals of the GOL chip are dis played in Figure 3. The signals can be
divided into several groups:
? Configuration data pins
Reference clock
Transmit data and transmit control s ignals
I2C interface
JTAG interface
High speed serial output signals
? Test
reset_b
Active Í0Î master reset signal.
ready
This signal indicates that the chip is in the READY state. In this state, the data
available on the input data bus Í din<31:0> Î is transmitted.
clkLHC
40.08 MHz LHC reference clock - single ende d input.
GOL
reset_b
ready
clkLHC
din<31:0>
cav /tx _ er
dav
/ tx_en
flag<1:0>
force_ff0
i2c _ adr<6:1>
SCL
SDA
JTAGRST_b
JTAGCLK
JTAG TMS
J TAGTDI
JTAGTDO
test_shift
serial_l aser
serial_line_p
serial_line_n
(test_anal og)
conf _ glink
conf
_wmode16
conf
_laser
conf
_negedge
conf
_i_
pll<2:0>
conf
_i_
ld
<2:0>
Config
data
TX data
andcontrol
I2C bus
JTAG
inte rface
High speed
serial output
Figure 3 ASIC external signals overview.
<1:0>
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clkLHCp, clkLHCn
40.08 MHz LHC reference clock signals Ð dif ferential input
conf_glink
Selects G-Link (CIMT encodi ng) mode when Í1Î, or Ethernet (8B/10B encoding)
mode when Í0Î. (Pull-up resistor).
conf_wmode16
Selects slow (16 bit input, 800 Mbit/s) m ode when Í1Î, or fast (32 bit input, 1.6 Gbit/s)
mode when Í0Î. (Pull-up resistor)
conf_laser
Selects serial laser driver output when Í1Î , or differential 50 ? line driver when Í0Î.
(Pull-up resistor)
conf_negedge
Selects clock edge to validate input data o n din<31:0> bus. If Í1Î, din is validated on
the falling edge of clkLHC , otherwise on the rising edge. S ee Figure 4 and Figure 5.
(Pull-d own resistor)
conf_i_pll
Selects the phase-locked loop (P LL) charge pump current, provided that the
use_conf_regs bit in the Config3 register is set to Í0Î. Otherwise, the value is directly
taken from the PLL_current bits of the configuration-register Í Config2 Î. (Pull-down
resistor)
conf_i_ld<1:0>