UMHE-http://atlas.physics.lsa.umich.edu/docushare

CSM-0 Users Manual

University of Michigan

April 22, 2004

B. Ball, J. Chapman, J. Gregory, J. Mann, and J. Hollar

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CSM Users Manual

OVERVIEW OF DESIGN

The CSM-0 (a prototype CSM) is documented

1 in this specification as a first step

toward the overall ATLAS muon front-end design that incorporates on-chamber data

concentrators. See the documents on the DocuShare server linked via ATLAS Electron-

ics > MDT Electronics and called “Options for MDT Connections” and “Program for

CSM Simulation and Design”. The general characteristic of the design has not changed

and is specified in numerous ATLAS muon publications as the near chamber part of the

NIMROD

2. This document describes the VerilogHDL simulation of the CSM and the

follow-on prototype module being designed from the simulation. This work, along with

a similar VerilogHDL description of the AMT-0.1

3 and AMT-1/2

4 will when a similar

description of the MROD is complete, provide a tool for continuously evaluating the

design as it matures. The prototype CSM-0 synthesized from the current VerilogHDL

code will serve as an active test fixture for the design. Its correctness can be confirmed

and the assumptions regarding the size and power consumption of the on-chamber data

concentrator can be verified. The prototype is built as a 6U VME module containing the

1. http://atlas.physics.lsa.umich.edu/docushare/default.htm

2. http://umaxp1.physics.lsa.umich.edu/~chapman/atlas/nimrod.ps

3. /afs/cern.ch/user/c/christia/public/atlas_tdc/doc/amt0_manual.ps

4. http://www-atlas.kek.jp/tdc/amt2/index.html

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Overview of Design

CSM Users Manual 1

CSM unit, a JTAG interface, an LHC clock emulation (a TTCrx

5 emulation with an

external trigger called the TTCem circuit), and a VME readable output FIFO.

The expected differences between the CSM unit mounted on chambers (called the on-

chamber unit) and the prototype CSM-0 are significant. The final on-chamber version

will be simpler in that it will not need to perform event building. Since the MROD must

form events from 6 CSM output streams, there is no need to do this job twice. The on-

chamber CSM will therefore be expected to do simple time-division multiplexing of

data from the 18 TDCs. With this scheme the source TDC can be determined from the

word position in the time sequence. If no data is available from a specific TDC, an idle

identifier will need to be sent. The hardware of the CSM-0 can be made to operate in

this mode and test of this algorithm will be implemented with the CSM-0. The full event

building version of the CSM-0 can be thought of as a CSM/MROD unit that handles

only one chamber in contrast to the final system which will incorporate six simple time

multiplexing CSMs feeding a six input MROD module (called an MROD) where the

event building will take place. Thus, the on-chamber CSM will not have a trigger ID

FIFO, a deep input FIFO, or a word count FIFO. It will have an optical output encoder

and driver to send 32-bit words to the MROD module (MROD) that accepts its output

and the output from 5 other CSM modules.

The overall flow of data from the chamber wires up to the modules in the Tower Sum-

mary Crate is represented in Figure_1 below. The simulation of the CSM must contain

the 18 TDC inputs each with their own serial data and serial strobe. It must describe the

output flow of data along the channel destined for the MROD. Data units are to be col-

lected from the TDCs by the CSM and transmitted in turn to the MROD modules

(MRODs). Data is to be transmitted from the CSM as 32-bit units serialized on a single

fiber. The 32-bit data units are either TDC headers, trailers, time digitizations, error

reports, and mask words. The source of each data unit is defined by its location in the

data stream. The primary task of the final CSM is that of time-division multiplexing.

Data from each TDC is sent as requested by the level 1 trigger when the front-end link

from the individual TDC becomes free,

i.e.

, when data from all previous triggers are

sent. Individual events are separated by header and trailer words. These header and

trailer words are selectively enabled for transmission by the TDC. At least trailer words

are required to indicate the end of event. The simulation assumes that both headers and

trailers are sent for redundancy.

FIGURE 1.

The Position of the CMS in the muon data flow.

5. http://www.cern.ch/Atlas/GROUPS/FRONTEND/Ttc1.htm

CSM

MROD

Mezzanine Card

Chamber Service Module

Tower Summary Crate

Containing MROD Cards

18/CSM

6/MROD

In Faraday cage 1 per chamber 1 MROD Card/TgrTower

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Design Specifications

2 CSM Users Manual

For the event building CSM-0 the situation is more complicated. The EVID from a

TTCem circuit must be used by the CSM-0 to anticipate data from a specific event and

to set an error condition when the data arriving is not consistent with the EVID

expected. As the CSM receives the header with the appropriate EVID from each TDC, it

begins assembling an event for that EVID. An option is provided so that the CSM can

pass or delete headers from the TDC after they are checked. Data assembled for an

event is forwarded to the readout FIFO on the VME card. A single CSM header will be

sent to the FIFO when a particular EVID is accepted by the CSM-0. When all TDCs

have completed transmission of the required event, the CSM-0 will flag the event with a

CSM-0 event trailer containing a word count for the event and begin assembling the

next event. The basic flow of information is illustrated in Figure_2 below.

FIGURE 2.

Serial data flow and event assembly by the CSM

DESIGN SPECIFICATIONS

Control Sequences

The CSM-0 will have need for at least 5 control sequences.

1.

Input from the TDCs will arrive as a serial bit stream that will be assembled into 32-

bit words under the control of a sequence that seeks a start bit, assembles 32 data

bits, tests a parity bit, and outputs the 32-bit data word with an output strobe.

2.

A second sequence will control the storing of EVIDs in the local trigger FIFO within

the CSM-0. At reset this FIFO is cleared and when data taking is enabled, a level 1

trigger from the TTCem will enter the EVID into a local trigger list.

TDC

TDC

TDC

TDC

9

9

8

8

8

7

9

10

10 9

8

7

8

8

9

9

10

9

10

9

10

11

CSM

Header

Data

Trailer

8

8

CSM Header

CSM Trailer

7

CSM Trailer

18 TDCs maximum

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Design Specifications

CSM Users Manual 3

3.

Another control sequence polls the Serial to Parallel outputs and enters any found

data into the accumulators (first-in first-out buffers). Polling must be round-robin

and loop in less than the 36 ticks of the clock since this time corresponds to the serial

shift time for one 32-bit data unit.

4.

When data exists in the local trigger FIFO and no event is being assembled and

transmitted to the output FIFO, the oldest EVID is extracted from the EVID list and

the data for this next event is sought for transmission to the output FIFO. A CSM-0

header is the first data unit sent.

5.

A final sequence controls the extraction of data from the input FIFOs of the individ-

ual TDCs for presentation to the output FIFO located on the VME card. Readout of

the VME based FIFO is described later. When data from all TDC has been received,

i.e.

, when all TDC trailers have been received and sent to the VME FIFO, a CSM-0

trailer is sent with the word count for the complete event. At this time the EVID and

event word count are entered into a VME readable FIFO and an event ready flag is

set.

The Block Diagram

The subsections of the CSM-0 are illustrated in Figure_3 below and described in the

sections that follow. The control sequences (Ctrl#n) involved with loading, emptying

and moving data between the various blocks are indicated.

FIGURE 3.

The Block Diagram of the CSM.

Serial to Parallel

The TDC resets to no data transmission and sends a steady stream of zero data and a

synchronous data strobe. The reset is derived from the TTCem and is also received by

the CSM-0. It should reset and ignore any previous activity on the input lines from the

TDC. An internal reset within the CSM-0 will provide for a quiescent state after a reset.

The first non-zero data following this quiescent state signals data to follow. When all

32-bits of the word are assembled into a shift register, the parity is read and tested.

When the parity is sampled, the 32-bit data word is sent to a 32-bit output register and

the input control sequence is returned to the reset state. If the parity test fails, an error bit

is set. When the parity is tested, an output data ready flag is set indicating that the 32-bit

Serial to Parallel

Accum

FIFO

18 to 1 Multiplexer

Serial to Parallel

18 Total

TDC

To

Accum

Ctrl#2

EVID List

Ctrl#3

VME

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Design Specifications

4 CSM Users Manual

output register contains data. This register cannot change more than once every 36 bit

times since the data stream contains a start bit, 32 data bits, parity bit, and two stop bits.

Sampling occurs each clock tick and advances to the next channel after each test so each

channel is examined every 18 ticks.

Input Accumulation

The 32-bit data words from the 18 TDCs arrive based on the data present in the TDCs

and the availability of their individual output sequencers. Therefore, although they send

all data for a given EVID before processing the next, data from a given TDC does not

have a well defined timing relationship to data for the same EVID from other TDCs.

Input FIFOs for each TDC are required to provide buffering of the disparate and disjoint

flow from individual TDCs. The required depth of these 18 FIFOs was the major goal of

this simulation study. Data is entered into a given TDCs FIFO when the Serial to Paral-

lel unit indicates a word is available. Data is extracted when the CSM finds a match

between the EVID of its trigger list and contained in the TDC header. The 18 accumula-

tion FIFOs can be implemented in RAM with 18 input addresses pointers and 18 output

address pointers. In this scheme the FIFO for a given TDC is empty when the output

address equals the input address. Full is indicated when an increment of the input

address makes the output address equal to the input address. Full is cleared whenever

output is incremented. Data is not to be written when a full flag is set. In this case an

error bit is set. To prevent data loss the content of the individual channel FIFOs is to be

monitored and triggers inhibited when the occupancy exceeds a programmable thresh-

old. All FIFOs of the CSM have fixed depth and a trigger inhibit is set when their con-

tents exceed a programmed threshold. Each threshold can be programmed up to the full

depth. The trigger and EVID/Word Count FIFOs are 16 locations deep. The TDC input

FIFOs are 512 words deep.

Event Building

(Multiplexing)

It is expected that both header and trailer words will be enabled in the TDC. These

header and trailer words each contain the EVID. The CSM-0 will have its own copy of

the expected EVID words, stored in a local trigger list FIFO when signaled by the level

1 accept from the TTCem. Each module along the readout chain thus saves entries in a

list of EVID numbers and can match these saved EVID numbers to those contained in

the data stream arriving from devices earlier in the data chain. Since the design require-

ments specify that all data with a given EVID number be transmitted before data from a

new EVID is sent, no data will arrive out of order. A mismatch of the EVID at any point

should be considered to be an error and should be flagged as such.

The CSM-0 will contain a control sequence that when reset will await level 1 triggers

and when received will store the EVIDs in its trigger queue. If one or more triggers exist

in the queue, the earliest one will be selected and a CSM-0 header will be sent to the

output FIFO to signal the beginning of a new output EVID. At this point headers for the

new EVID will be sought from each of the 18 TDCs presenting data to the CSM-0. As

headers with the appropriate EVID are seen from each TDC, these headers (optionally)

and data following them will be queued to an output FIFO for transmission from the

CSM-0 to the VME based FIFO. This transmission sequence will continue up to and

optionally including the trailers from the TDCs for the EVID. When the trailers with the

proper EVID from all 18 TDCs have been detected (and optionally sent to the output), a

CSM trailer with the EVID will then be attached to the end of the output data for the

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Design Specifications

CSM Users Manual 5

current EVID. The CSM-0 trailer will contain the word count for the entire event. The

EVID and word count for the completed event will also be entered into a FIFO readable

over VME to provide the readout with a word count and EVID to expect when the VME

data FIFO is read. Processing of data into the output FIFO will be disabled at this point

and a new level 1 trigger EVID sought from the trigger list FIFO.

An error occurs when the trigger EVID does not match that seen from any TDC. If a

header is seen with an incorrect EVID, the event and/or its header is missing. If a trailer

is seen with an incorrect EVID, the event has been mixed with another or its trailer is

missing. If a trailer is seen when a header is expected, the header and possibly data is

missing. If a header is seen when a trailer is expected, the trailer and possibly data is

missing. A CSM-0 error word is defined to specify these error conditions. The CSM-0

header, trailers, and error word contain a unique ID code. The CSM-0 contains a general

form of error processing to permit continuous event flow in the case where an event is

seen to be incomplete. This code is arranged to continue processing events when the

EVID being assembled into an event is incomplete while at the same time all TDCs

have presented data to the unit. If this data, seen residing in the input FIFO, is recog-

nized as not being from the current event, then the current event will never finish nor-

mally. The TDCs send all data for one event before sending any data for others. In this

fault case, the CSM-0 will terminate the event with an error word containing flags from

all TDCs that are missing a header or trailer. The CSM-0 will also flag this abnormal

termination in the subID of its trailer.

The output of the CSM-0 is to be sent as 32-bit data units to a VME readable FIFO or, in

the case of the final CSM, to a fiber encoder/driver. The next step in the simulation pro-

cess is essentially a repeat of the CSM-0 simulation and development configuring the

code as a fast 6 to 1 multiplexer with similar EVID matching to a trigger list. Since the

MROD unit is expected to perform the event building from multiple sources, the CSM

based event building will no longer be required. In this case the CSM can and will oper-

ate in a transparent mode making no tests of the EVID and BCID values. To identify the

source TDC of data within the stream, time division multiplexing has been suggested. In

this scheme, each of the 18 TDC is identified with a position within a pattern of 18 con-

secutive time slots. The TDC header/trailer word design contains 4 bits of TDC number.

This 4 bit number can be checked with the time division slot allocation to verify that the

data from each TDC is correctly positioned in the time slot. Alternately, since the CSM

must transmit something during “idle” times when a given TDC has no data to transmit,

the CSM might naturally send an “idle” code in its ID section with the TDC source

located in the remaining bits during idle times.

Data Word Formats

The data words from the TDC are described in the AMT-1/2 document

6 and summa-

rized below in Table 1. Note that the header and trailer words from the TDC provide the

EVID and the BCID words. The location of these bits permits a check of the data arrival

consistency as described above. The CSM headers and trailers are defined similarly.

The TDC data words also contain an error bit that indicates when data has been missed.

The data miss bit is to be interpreted as a flag that data was lost between the time of the

6. http://www-atlas.kek.jp/tdc/amt2/index.html

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Design Specifications

6 CSM Users Manual

last data unit without a flag set for a given TDC and the data units with flags for that

TDC. CSM error reporting is accommodated as a subtype of the CSM ID since there are

28 bits available for CSM data, the highest bit of the 28 is devoted to a flag that distin-

guished the errors from the CSM headers and trailers. The error word has a bit for each

of the 18 TDCs with an error code of 9 bits. To date, only one CSM-0 error, auto termi-

nation of incomplete events is defined. CSM header, trailer, and error word are specified

in the table below.

Another task of the prototype CSM will be to accommodate the presence of 18 TDCs in

a data format that has a 4 bit field for the TDC. This can be accomplished by combining

the 4-bit TDC field with the 5-bit channel number into a 9-bit wire number for the

chamber. Since there is a maximum of 18, 24-channel TDCs, there is a maximum of 432

total channels. This can easily fit in the 9-bit field. The simplest encoding is probably to

encode the first 16 TDCs as TDC number 0-15 with channels 0-23. For TDC 16 the first

8 channels are mapped to TDC 0 channels 24-31, the second 8 channels to TDC 1 chan-

nels 24-31, and the final 8 channels to TDC 2 channels 24-31. TDC 17 are similarly be

mapped to the high channels of TDC 4, 5, and 6. The high channels of TDC 3 and 7

would not contain data in this scheme. Other schemes of mapping are possible but are

more or less equivalent.

TABLE 1.

TDC & CSM Word IDs expected & sent in normal data taking mode

ID Word Contents Depends on ID Type

31-28

2

7

2

6

2

5

2

4

2

3

2

2

2

1

2

0

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

9

8

7

6

5

4

3

2

1

0

1010

TDC EVID BCID

1100

TDC EVID Word Count

0010

TDC Mask Flags

0011

TDC Channel T E Coarse Time Fine Time

0100

TDC Channel Width Coarse Time Fine Time

0110

TDC Unused Errors

0111

TDC 0000 BCID

0111

TDC 0001 R L1 Occupancy

CSM output formats defined to date

0101 1001

EVID BCID

0101 1011

EVID Word Count

0101

1101

a

a. This subID flags an abnormal event termination which is proceeded by the error word

with subID zero.

EVID Word Count

0101 0

Error Code Abnormal TDC

1010

TDC EVID BCID

1100

TDC EVID Word Count

0011

Wire Number T E Coarse Time Fine Time

0100

Wire Number Width Coarse Time Fine Time

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The CSM-0 Module Specifications

CSM Users Manual 7

Some data in Table 1 above is modified in diagnostic mode, DIAG2 = 1, such that CSM

header contains diagnostic data in place of the BCID value. This diagnostic word con-

tains data according to Table 2. In addition, all word IDs received are passed in DIAG2

= 1 mode. The unrecognized IDs and the remaining contents of the words are

unchanged in the forwarding process.

Other diagnostic features are included as well. If DIAG0 = 1, the CSM-0 makes no test

of BCID matching between the TDC headers received from the TDC and the BCID

present in the trigger sent to the CSM event builder by the TTCem. If DIAG1 = 1, no

test of EVID matching is done. In this latter case, events are built from the next header,

data, trailer block received from each TDC. For running with cosmic ray data, one nor-

mally sets DIAG0 = 1 and DIAG1 = 0 since the EVID is meaningful but the BCID is

just data from free running counters in the TDC and TTCem. With careful programming

of the rollover and reset values for the TDC and TTCem counters, a match can be

required between the BCID value as well.

To permit a low level diagnostic to be run, a programmable bit, “pass”, can be set. This

bit is only active if data taking has been halted (active = 0). When active = 0 and pass =

1, any event waiting to complete is forced to complete with an CSM error word contain-

ing flags from all TDCs that have not completed. The CSM trailer will also send an

ID=5d instead of 5b in this error case. When this mode is used and a failure of the sys-

tem to complete an event is observed (a time-out for example), data taking is to be set

inactive, “pass” is set, the forced completion is examined, and data taking is resumed,

possibly after a global reset.

An automatic activation of this feature is also implemented, as mentioned previously,

such that if an event has not completed because (all enabled TDCs have not sent both

headers and trailers for the current event), but all TDC have presented additional event

data to the CSM, the incomplete event is terminated with the same error conditions as

with the “pass” terminated event. Thus, if a single TDC’s header is missed, the event

will complete when the next event is ready to be assembled.

THE CSM-0 MODULE SPECIFICATIONS

Components Needed

The CSM-0 is designed as a test bed for the data concentrator VerilogHDL in essentially

the form that it will be configured for a real on-chamber CSM unit. The difference being

that the CSM-0 does event building and the CSM will not since event building will need

to be done in the modules of the MROD and need not be done twice. The on-chamber

TABLE 2.

Diagnostic mode CSM Header word lower 12 bits

CSM Header BCID Field in DIAG2 = 1 Mode

11

-

6 5

4

3

2

1

0

0 Serial Error Trigger FF Stop WC FF Stop Data FF Stop Data FF Full Ext FF Stop

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The CSM-0 Module Specifications

8 CSM Users Manual

unit will work in conjunction with the TTCrx (trigger, timing, and control chip), with an

external JTAG controller (probably one implemented in an FPGA) whose JTAG loop

includes the TDCs and ASDs, and with a fiber output to the MROD in place of the read-

out FIFO of the CSM-0 as described below. The CSM-0 must include some trigger, tim-

ing, and control element and a JTAG controller since these elements are not part of the

Xilinx chip that contains the prototype CSM. The VME card must also have some data

storage in which to put the event data that the on-chamber CSM would normally deliver

to a fiber driver. The CSM-0 components are therefore:

• An oscillator to generate a 25ns clock which emulates the LHC beam crossing cycle.

• A control circuit that serves to emulate the TTCrx and accepts an external trigger.

This will be a single Xilinx distinct from the one that performs the data collection.

• A second Xilinx that accomplishes the multiplexer part of the data collection, the

real” CSM.

• Three smaller Xilinx chips perform the serial to parallel conversion, each perform-

ing the task for 6 channels.

• A JTAG interface that connects to the five Xilinx chips and to the TDCs that feed

data to the CSM-0 module. A single loop is included in the prototype.

• An external FIFO that accepts the data from the output of the CSM.

• A VME interface that controls the JTAG functions, CSM functions, TTCrx emula-

tion, and the FIFO readout.

• LVDS drivers and receivers that deliver the clock and encoded control signals to the

TDCs and receive the data and strobes from the TDCs.

• Both NIM and ECL trigger inputs that are ORed together to form the trigger sent to

The block schematic of the CSM-0 is below in Figure_4.

FIGURE 4.

CSM-0 Block Schematic

ASD/TDC

CSM

Data

Mux

ASD/TDC

ASD/TDC

ASD/TDC

VME I/O

FIFO

TTC

Functions

ECL/NIM

Trigger

Input

CSM-0

JTAG

Clk, Lvl 1,

JTAG, Data

DS Clk

LVDS Convertors

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The CSM-0 Module Specifications

CSM Users Manual 9

The number of TDC units needed for the largest chambers is 18. For chambers with less

than the maximum number of wires, the CSM-0 trigger source time can be digitized in

the unused TDC inputs. A single unused TDC slot can provide up to 24 scintillator

times. For the largest chambers, an additional CSM unit can be used to provide addi-

tional TDC inputs to handle the trigger scintillator outputs. The CSM unit will output 2

copies of its 25ns crystal oscillator and input its clock so that two CSM units can use the

same oscillator and thus operate with the same common timing reference. Care will

need to be taken to insure that the 2 replications of the oscillator signal have similar

cable delays within the timing resolution expected. In all configurations the digitization

of the trigger sources will provide for the determination of a common t0 for the drift

tubes. This t0 is not naturally available in a system where the timing depends on a free

running clock unrelated in time to the external trigger. The trigger signal will be syn-

chronized with the leading edge of the clock and can as a result have a random 25ns

variation.

The Oscillator

A 25ns period TTL oscillator is needed with adequate LVDS fanout to drive the 18 TDC

signals. Two copies of it will be directed first to a front panel connector which can be

jumpered back into the module clock input. This routing scheme permits all modules in

a multi-module system to use the same oscillator. The logic level for the exiting and

returned clock will be TTL. The returned clock will need to be routed to the Data Mux

Xilinx and to the TTC emulator.

The TTC Emulation

The TTC emulator Xilinx (TTCem) has the following functions:

• The TTCem must receive the external trigger and synchronize it to the next full

width clock if no level 1 trigger has been sent in the last 5 clock cycles. If the separa-

tion condition is met,

i.e.

, a good trigger is seen, a delay of the clock of up to 127

clock ticks is initiated, an encoded level 1 trigger is then sent to the TDCs, and sent

unencoded to the Data Mux Xilinx. The EVID described below is incremented after

the level 1 trigger is sent to the TDC.

• The TTCem must include an 12-bit EVID counter that is incremented with each

good level 1 accept. This EVID is sent to the Data Mux for storage in its trigger

FIFO. The EVID is preset by a ECprst signal. The preset value is programmed

through VME. The ECprst must also be synchronized to the next full width clock

and sent encoded to the TDCs as specified in the AMT-0.1 manual.

• The TTCem must include a 12-bit BCID counter that is incremented at each clock

tick. The BCID rolls over to zero at a preloaded count. This rollover count is preset

by a BCprst from VME. The BCprst is to be synchronized with the next full clock

and sent to the TDCs encoded as specified in the AMT-0.1 manual.

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The CSM-0 Module Specifications

10 CSM Users Manual

• The TTCem must disable triggers on a enable/disable from VME and on reception

of a stop signal from the CSM multiplexer. Stop is generated from the OR of the

individual FIFO stop signals. The Trigger ID FIFO sets stop can be programmed

from 0 to 15 events of the possible 16 locations. If the number of triggers received

but not processed exceeds the programmed threshold, triggers are disabled. The 18

CSM input FIFOs assert their stop signals at a 9-bit programmable value between 0

and 512 of the 512 locations and the external FIFO exerts its stop at 16K - 1024

locations.

The Data Multiplexer

The Data Mux Xilinx (the “real” CSM-0) needs to:

• Implement the CSM-0 data buffering and data mux according to the VerilogHDL

code previously described.

• Accept the EVID and BCID from the TTCem along with the level 1 accept, store

these numbers in a trigger FIFO, and extract, in turn, triggers from the FIFO, send a

CSM header with the EVID and BCID, and await the TDC headers for the EVID.

When a header arrives from a specific TDC, check it for EVID consistency.

• Optionally send to the output FIFO the TDC header with its EVID and BCID or sup-

press it depending on the option selected over VME. Save in a flag bit the fact that

the header has arrived from each TDC separately.

• Pass data words from each TDC that has delivered its header with the correct EVID

onto an output FIFO.

• Encode the TDC source number and TDC channel number into a 9-bit wire number

where the TDC with source number 0-15 encodes as TDC 0-15 with channel num-

bers 0-23 and TDC source number 16 encodes as TDC 0,1,2 with Channels 24-31,

and TDC source number 17 encodes as TDC 4,5,6, Channels 24-31.

• Reset all header seen flags on overall Reset. Clear all data within the trigger FIFO,

input FIFOs, and output FIFO as well. Disable triggers on these reset signals.

• Count the number of words sent to the output FIFO for the current EVID and upon

completion of the transfer for the current EVID, send this word count along with the

EVID to a shallow FIFO whose output can be read over VME prior to starting a

Block Transfer from the output FIFO over VME. Event completion is flagged by the

transmission of the CSM trailer which also contains the EVID and word count.

• Support 18 status bits indicating the arrival of the appropriate TDC header words,

one for each TDC. Check these flags against the TDC enable flags to determine

TDC completion.

• Support 18 status bits indicating the arrival of the appropriate TDC trailer words,

one for each TDC. Check these flags against the TDC enable flags to determine

TDC completion.

The JTAG Interface

The JTAG interface contains a National SCANPSC100F controller chip which provides

2 JTAG or other serial bus connections. The SCANPSC100F is a flexible 8-bit parallel

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The CSM-0 Module Specifications

CSM Users Manual 11

loaded serial bus controller which will execute a very general class of serial protocols.

7

The National chip occupies 8 32-bit locations in VME space. Some of the data bits have

different definitions for read and write making the R/W bit look like another address bit.

A simple program I/O connection from VME to the controller is all that is implemented.

Programming for the controller is outlined below. The PPI (parallel processor interface)

has very simple control with an OE, CE, STB (connected to DS), RST, RDY (connected

as DACK, and INT. The three lower address bits go to the A(4:2) pins to select the cor-

rect register and R/W from the VME connects to the chip R/W line. An external clock is

to be supplied. It is convenient to use the 40Mhz oscillator that emulates the LHC beam

crossing. When divided by 2 a total of 8 times, this oscillator provides 8 frequencies

from 20MHz to 158kHz. An 8 to 1 multiplexer follows the divider with a programmable

selection of 1 of 8 frequencies from the range. However, since the SCANPSC100F has a

maximum of 25Mhz clock speed the original 40MHz clock cannot be used. Output

Enable is wired low so that the chip is always enabled. Chip Enable is connected to the

address range selecting the PPI” signal from the Cypress VME controller.

The External FIFO

An external 32-bit FIFO receives data from the CSM output, one 32-bit data word every

clock if any data is available from the CSM. The external FIFO can be formed from one

of the commercial FIFOs that are marketed as a series in various depths. A rather large

size has been chosen since it offers the greatest flexibility for filling and emptying. A

FIFO of 16K depth is used. The FIFO is controlled by the Data Mux Xilinx which sends

the FIFO data on every clock when data is present and the external FIFO has room. The

external FIFO is 16K deep and triggers are inhibited when it is within 1023 words of

full, a overflow is unlikely and the FIFO full will probably never inhibit transfers.

Programming the Flow of Data

Data in this system flows from output FIFOs of the TDC chips to the CSM input FIFOs,

through the Multiplexer, into an large on-board FIFO, and is read from this FIFO over

VME. To study the behavior of this flow when various FIFOs contain large amounts of

data, several control bits are provided to block the processing of data along the path.

The first of these is the trigger enable/inhibit. With this bit set to inhibit, the sending of

events from the TDC will cease at the completion of all previously triggered events.

Data already in progress at various points along the flow will continue to be processed if

the other block points are still in pass mode. This inhibit is automatically generated

when the CSM-0 input FIFOs fill to within its preset number of words.

A second point where data can be blocked is at the entry to the CSM input FIFOs. To

disable all TDCs, the individual TDC enables can be all set to false. Since the serial

transmission will continue in this situation, the data arriving at the CSM will simply be

lost. A third inhibit is provided at the polling multiplexer that processes data from the

CSM-0 input FIFOs. This inhibit bit is called the daq-inh bit of the CSM-0 enable word.

A block at this point will eventually result in FIFO overflows if triggers remain enabled.

7. http://www.national.com/

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The CSM-0 Module Specifications

12 CSM Users Manual

The final programmable inhibit exists at the data readout stage. This is accomplished by

ignoring the flag that represents Event_Ready. If the Event_Ready flag is ignored, the

software will cease reading events. These blocks along the flow will permit us to study

the surge of data when FIFOs are full and the block is released.

The VME Interface

The CSM-0 board has need for VME control of several registers and conditions. In

addition, the unit needs to have block-transfer capability for reading the data FIFO rap-

idly. Since VME requires a pre-defined word count for a block transfer to be done effi-

ciently and to terminate appropriately, a word count register is to be included at a

specific VME address. This word count is to be loaded from a shallow FIFO within the

Data Mux. Each entry into this FIFO represents the EVID and word count of the oldest

event not already read over VME. Thus, the VME sequence will be a programmed I/O

read of the word count (and EVID) register followed by a block transfer of the number

of words specified by the word count from the data register address. The VME card

operates in A32 D32 mode for this block transfer. The base address of the card is be

formed from switches that define the high address bits. If the FIFO is 16k locations

deep, the block transfer could, in principle move 16k words. The actual address incre-

ments from the base address would span 64k byte locations. Thus the VME interface

needs to be initialized to the starting address of the address range but the lower address

bits of the block transfer will not be used so that the FIFO address will always be

accessed. It is most natural that the 16k byte block be chosen on a natural address

boundary. The VME interaction for the registers contained within the multiplexer chip

is also handled within that same chip. This interaction is controlled by lines for subad-

dress, chip select, read/write, acknowledge, and a local data bus.

Addressing of the SCANPSC100F can follow the same offset address but the 8 bytes

are to be accessed individually as 32 bit units. Only the lower 8 bits will be meaningful.

The nature of these bytes is completely specified in the National chip document making

it quite simple to interface since the VME access is predefined for us.

The Hardware

The hardware is arranged on a 6U VME card which functions as the receiver for the

CSM. This replaces what will be a MROD channel connected to the CSM via a fiber

link. The link in this case is a pair of connectors/plugs that attach the CSM card to the

VME card. Two connectors are used for attachment stability and for access to many

diagnostic points not because all the pins are needed for communication. The CSM

daughter card has three deserialization chips, a TTCem chip, and a multiplexer chip. In

addition, there is an IDT dual ported RAM and a Cypress clock replicator. The output

FIFO is located on the VME card. The daughter card also contains a serial PROM for

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The CSM-0 Module Specifications

CSM Users Manual 13

downloading the Xilinx programs. The daughter card is attached to the VME card with

two 140 pin surface mount connectors and their mating plugs. These connectors are the

same used at Michigan for attachment of logic analyzer test fixtures making it possible

to examine the VME card signals without the daughter card attached. In addition, the

daughter card has two such connectors between the Xilinx chips on the outer side as test

fixture attachments. Essentially all signals on the VME card and daughter card are

accessible via these diagnostic connectors. An image of the VME card is shown below.

FIGURE 5.

The Front Panel of the CSM-0 Card

The attachment plugs are on the underside of the daughter card and are not visible. Vis-

ible in the photo above, however, are the front panel clock outputs, a clock input all in

Lemo format, a NIM trigger input, an ECL trigger input, the 18 TDC RJ45 style con-

nectors, and the 2 JTAG RJ45 connectors at the lower position (to the right in the

photo). The daughter card containing the TTCem, deserialization units, and multiplexer

is shown separately below.

JTAG Output

JTAG Input

FE Links

40MHz Clocks 40MHz Clock In

NIM Trigger

ECL Trigger