Verilog HDL Reference Manual

FPGA Compiler II /

FPGA

Express

Verilog HDL

Reference Manual

Version 1999.05, May 1999

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FPGA Compiler II / FPGA Express Verilog HDL Reference Manual, Ve rsion 1999.05

iii

About This Manual

This manual describes the Verilog portio n of Synopsys FPGA

Compiler II / FPGA

Express application, part of the Synop sys suite

of synthesis tools. F PGA Compiler II / FPGA

Express

reads an RTL

Verilog HDL model of a discrete electroni c system and synthesizes

this description into a gate-level netlist.

FPGA Compiler II / FPGA

Express supports v1.6 of the Verilog

language. Deviations from the d efinition of the Verilog language are

explicitly noted. Constructs added in ver sions subsequent to Verilog

1.6 might not be supported. Aspects of the Verilog language that are

not supported are listed in Appendix B.

Audience

This manual is written for logic designers and electronic engineers

who are famili ar with Synopsys synthesis products. Knowledge of the

Verilog language is required, and knowledge of a high-level

programming language i s helpful.

Other Sources of Information

The resources in the following sections provid e additional information:

• Related P ublications

• SolvNET Online Help

• Customer Support

Related Publications

These Synopsys documents supply additional inf ormation:

• FPGA Compiler II / FPGA E xpress Getting Started Manual

• Design Compiler Command-Line Interface Guide

• Design Compiler Reference Manual: Constraints and Timing

• Design Comp iler Reference Manual: Optimization and Timing

Analysis

• Design Compiler Tutorial

• Design Compiler User Guide

• DesignWare Developer Guide

• VSS User Guide

Man Pages

You can view man pages from fc2_shell / fe_she ll environment. From

the shell prom pt, enter:

fc2_shell> help command_name

fe_shell> help command_name

SolvNET Online Help

SOLV-IT! is the Synopsys electronic knowledg e base. It contains

information abou t Synopsys and its tools and is updated daily.

Access SOLV-IT! through e-mail or through th e World Wide Web

(WWW). For more inf ormation about SOLV-IT!, send e-mail to

solvitfb@synopsys.com

or view the Synopsys Web page at

http://www.synopsys.com

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Conventions

The following conventions are used in Synop sys documentation.

Convention Description

courierIn dicates command syntax.

In command syntax and examples, shows

system p rompts, text from files, error

messa ges, and reports printed by the

system.

courier italic Indicates a user specification, such as

object_name

courier bold In command syntax and examples, indicat es

user input (text the user types v erbatim).

[ ] Denotes optional parameters, such as pin1

[pin2, . . pinN]

|I ndicates a choice among alternatives, such

low | medium | high

This example indicates that you can enter

one of three possible values for an option:

low, medium, or high.

_ Connects two terms that are read a s a single

term by the syste m. For example,

design_space.

(Ctrl-c) Indicates a keyboard combination, such as

holding down the Ctr l key and pressing c.

\ Indicates a continuation of a comm and line.

/ Indicates levels of directory stru cture.

Edit > Copy Shows a menu selection. Edit is the menu

name and

Copy is the item on the menu.

vii

Table of Contents

About This Manual

1. FPGA Compiler II / FPGA

Express with Verilog HDL

Hardware Description Languages . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

FPGA Compiler II / FPGA

Express and the Design Process . . . . . 1-4

Using FPGA Compiler II / FP GA

Express

to Compile a Verilog HDL Design

1-5

Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2. Description Styles

Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Structural Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Mixing Structural and Functional Descrip tions . . . . . . . . . . . . . . . . 2-4

Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Description Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Language Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

viii

Asynchrono us Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

3. Structural Descriptions

Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Macromodules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Port Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Renaming Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Module Statements and Constructs . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Structural Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

wire. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

wand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

wor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

tri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

supply0 and supply1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Port Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

inout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Continuous Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Module Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Named and Positional Notation . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Parameterized Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Ga te-Level Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Three-State Buffer Instant iation . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

4. Expressions

Constant-Valued Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Relational Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Equality Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Handling Comparisons to X or Z . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Logical Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Bitwise Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Reduction Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Shift Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Conditional Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Concatenation Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Operator Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Wires and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Bit-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Part-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Concatenation of Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

Expression Bit-Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

5. Functional Descriptions

Sequential C onstructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Function Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Input Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Output From a Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Memory Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Parameter Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Integer Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Function Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Procedural Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

RTL Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

begin...end Block Statements . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

if...else Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Conditional Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

case Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

Full Case and Parallel Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

casex Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

casez Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

for Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

while Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

forever Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

disable Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

task Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

always Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

Ev ent Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

Incomplete Event Spec ification . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

6. Register and Three-State Inference

The Inference Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Latch Inference Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Controlling Register Inference . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Attributes That Control Register Inference . . . . . . . . . . . . . . 6-4

Inferr ing Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Inferring SR Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Inferring D Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Understanding the Limitations of D Latch Infer ence . . . . . . 6-19

Inferring Ma ster-Slave Latches. . . . . . . . . . . . . . . . . . . . . . . 6-19

Inferring Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Inferring D Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Understanding the Limitations of D Flip-Flop I nference . . . . 6-35

Inferring JK F lip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37

Inferring Toggle Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41

Getting the Best Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46

Understanding Limitations of Register Inferenc e . . . . . . . . . . . . 6-50

Thre e-State Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51

Reporting Three-Stat e Inference . . . . . . . . . . . . . . . . . . . . . . . . 6-51

Controlling Three-State Inference . . . . . . . . . . . . . . . . . . . . . . . 6-51

Inferring Three-State Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52

Simple Three-State Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52

Registered Three-State Drivers . . . . . . . . . . . . . . . . . . . . . . 6-57

xii

Understanding the Limitations of Three-State Inference . . . . . . 6-60

7. Writin g Circuit Descriptions

How Statemen ts Are Mapped to Logic . . . . . . . . . . . . . . . . . . . . . . 7-2

Design Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Using Design Knowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Optimizing Arithmetic Expressions . . . . . . . . . . . . . . . . . . . . . . 7-7

Arranging Expression Trees for Minimum Delay. . . . . . . . . . 7-7

Sharing Comm on Subexpressions. . . . . . . . . . . . . . . . . . . . 7-12

Using Operator Bit-Width Efficiently. . . . . . . . . . . . . . . . . . . . . . 7-15

Using State Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Describing State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Minimizing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

Separating Sequential and Combinational Assign ments. . . . . . 7-27

Don’t Care Infe rence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28

Limitations of Using Don’t Care Values . . . . . . . . . . . . . . . . . . . 7-29

Differences Between Simulation and Synthesis. . . . . . . . . . . . . 7-29

Propag ating Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Synthesis Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Feedback Paths and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Synthesizing Asynchronous Designs. . . . . . . . . . . . . . . . . . . . . 7-32

Designing for Overall Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34

Describing Random Lo gic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35

Sharing Complex Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35

xiii

8. FPGA Compiler II / FPGA Express Directives

Notation for FPGA Compiler II / FPGA

Express

Directives . . . . . . . 8-2

translate_off and translate_on Directives . . . . . . . . . . . . . . . . . . . . 8-2

parallel_case Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

full_case Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

state_vector Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

enum Directive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

Component Implication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

A. Examples

Count Zeros—Combinational Version . . . . . . . . . . . . . . . . . . . . . . . A-2

Count Zeros—Sequential Version . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

Drink Machine—State Machine Version . . . . . . . . . . . . . . . . . . . . . A-7

Drink Machine—Count Nickels Version. . . . . . . . . . . . . . . . . . . . . . A-10

Carry-Lookahead Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12

B. Verilog Syntax

Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

BNF Syntax Formalism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

BNF Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Lexical Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

White Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13

Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13

xiv

Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13

Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

Macro Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16

include Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17

Simulation Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18

Verilog System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18

Verilog Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19

Unsupported Verilog Language Constructs. . . . . . . . . . . . . . . . . . . B-20

xvi

xvii

List of Figures

Figure 1-1 FPGA Compiler II / FPGA

Express

Design Process. . . . 1-4

Figure 1-2 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Figure 3-1 Structural Parts of a Module . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 5-1 Schematic of RTL Nonblocking A ssignments . . . . . . . . . 5-13

Figure 5-2 Schematic of Blocking Assignme nt. . . . . . . . . . . . . . . . . 5-14

Figure 6-1 SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Figure 6-2 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Figure 6-3 D Latch With Asynchronous Set. . . . . . . . . . . . . . . . . . . 6-15

Figure 6-4 D Latch With Asynchronous Re set . . . . . . . . . . . . . . . . . 6-16

Figure 6-5 D Latch With Asynchronous Se t and Reset . . . . . . . . . . 6-18

Figure 6-6 Two-Phase Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Figure 6-7 Positive Edge-Triggered D F lip-Flop . . . . . . . . . . . . . . . . 6-23

Figure 6-8 Negative Edge-Triggered D Flip -Flop . . . . . . . . . . . . . . . 6-24

Figure 6-9 D Flip-Flop With Asynchrono us Set . . . . . . . . . . . . . . . . 6-25

Figure 6-10 D Flip-Flop With Asynchrono us Reset . . . . . . . . . . . . . . 6-26

Figure 6-11 D Flip-Flop With Asynchrono us Set and Reset . . . . . . . 6-28

xviii

Figure 6-12 D Flip-Flop With Synchronous Set . . . . . . . . . . . . . . . . . 6-30

Figure 6-13 D Flip-Flop With Synchronous Reset . . . . . . . . . . . . . . . 6-31

F igure 6-14 D Flip-Flop With Synchronous and Asynchronous Load 6-33

Figure 6-15 Multiple Flip-Flops With Asynch ronous and Synchronous Controls

6- 35

Figure 6-16 JK Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

Figure 6-17 JK Flip-Flop With Asynchronous Se t and Reset. . . . . . . 6-41

Figure 6-18 Toggle Flip-Flop With Asynchronous Set . . . . . . . . . . . . 6-43

Figure 6-19 Toggle Flip-Flop With A synchronous Reset . . . . . . . . . . 6-44

Figure 6-20 Toggle Flip-Flop With Enable and A synchronous Reset. 6-46

Figure 6-21 S chematic of Simple Three-State Driver . . . . . . . . . . . . 6-53

Figure 6-22 One Three-State Driver Inferred Fr om a Single Block . . 6-55

Figure 6- 23 Two Three-State Drivers Inferred From Separate Blocks 6-57

Figure 6-24 Three-State Driver With Register ed Enable . . . . . . . . . . 6-58

Fi gure 6-25 Three-State Driver Without Registered Enable. . . . . . . . 6-60

Figure 7-1 Ripple Carry Chain Implem entation . . . . . . . . . . . . . . . . 7-4

Figure 7-2 Carry-Lookahead Chain Implementati on . . . . . . . . . . . . 7-5

Figure 7-3 Default Expression Tree . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

Figure 7-4 Balanced Adder Tree ( Same Arrival Times for All Signals) 7-9

Figure 7-5 Expression Tree With Minimum Dela y (Signal A Arrives Last)

7-9

Figure 7-6 Expression Tree With Subexpre ssions Dictated by Parentheses

7-10

Figure 7-7 Default Expression Tree W ith 4-Bit Temporary Variable . 7-11

F igure 7-8 Expression Tree With 5-Bit Intermediate Result . . . . . . . 7-12

xix

F igure 7-9 Synthesized Circuit With Six Implied Registers . . . . . . . 7-25

Figure 7-10 Synthesized Circuit With Three Implied Registers . . . . . 7-26

Figure 7-11 Mealy Machine Schematic . . . . . . . . . . . . . . . . . . . . . . . 7-28

Figure 7-12 Circuit Schematic With Two Array Indexes . . . . . . . . . . . 7-37

Fi gure 7-13 Circuit Schematic With One Array Index. . . . . . . . . . . . . 7-39

Figure A-1 Count Zeros—Combinational Version Block Diagram . . A-4

Figur e A-2 Count Zeros—Sequential Version Block Diagram . . . . . A-7

Figure A-3 Drink Machine—State Machine Versio n Block Diagram . A-10

Figure A-4 Dri nk Machine—Count Nickels Version Block Diagram . A-12

Figure A-5 Carry-Lookahead Adder Block Diagram . . . . . . . . . . . . . A-14

xxi

List of Tables

Table 4-1 Verilog Operators Supported by FPGA Compiler II / FPGA

E xpress

4-3

Table 4-2 Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Table 4-3 Expression Bit-Widths . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

Table 6-1 SR Latch Truth Table (Nand Type ) . . . . . . . . . . . . . . . . . 6-8

Table 6-2 Truth Table for JK Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . 6-38

Table B-1 Verilog Radices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14

Table B-2 Verilog Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19

xxii

xxiii

List of Examples

Example 2-1 Mixed Structural and Functi onal Descriptions. . . . . . . 2-5

Example 3-1 Module Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Example 3-2 Macromodule Construct . . . . . . . . . . . . . . . . . . . . . . . 3-3

Example 3-3 Module Port Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Example 3-4 Renaming Ports in Modules . . . . . . . . . . . . . . . . . . . . 3-6

Example 3-5 parameter Declaration Syntax Error . . . . . . . . . . . . . . 3-9

Example 3-6 parameter Declarations. . . . . . . . . . . . . . . . . . . . . . . . 3-9

Example 3-7 wire Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Example 3-8 wand (wired-AND). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Example 3-9 wor (wired-OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Example 3-10 tri (Three-State). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Example 3-11 supply0 and supply1 Construc ts . . . . . . . . . . . . . . . . . 3-13

Example 3-12 reg Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Example 3-13 Two Equivalent Continuous As signments . . . . . . . . . . 3-15

Example 3-14 Module Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Example 3-15 parameter Declaration in a Module . . . . . . . . . . . . . . . 3-20

xxiv

Example 3-16 Gate-Level Instantiations. . . . . . . . . . . . . . . . . . . . . . . 3-21

Example 3-17 Three-State Gate Instantiation . . . . . . . . . . . . . . . . . . 3-22

Example 4-1 Valid Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Example 4-2 Addition Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Example 4-3 Relational Operator. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Example 4-4 Equality Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Example 4-5 Comparison to X Ignored . . . . . . . . . . . . . . . . . . . . . . 4-7

Example 4-6 Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Example 4-7 Bitwise Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Example 4-8 Reduction Operators. . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Example 4-9 Shift Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Example 4-10 Conditional Operator. . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Example 4-11 Nested Conditional Operator. . . . . . . . . . . . . . . . . . . . 4-13

Example 4-12 Concatenation Operator . . . . . . . . . . . . . . . . . . . . . . . 4-14

Example 4-13 Concatenation Equivalent . . . . . . . . . . . . . . . . . . . . . . 4-14

Example 4-14 Wire Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Example 4-15 Bit-Select Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Example 4-16 Part-Select Operands . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Example 4-17 Function Call Used as an Operand. . . . . . . . . . . . . . . 4-18

Ex ample 4-18 Concatenation of Operands . . . . . . . . . . . . . . . . . . . . 4-19

Example 4-19 Self-Determined Ex pression . . . . . . . . . . . . . . . . . . . . 4-21

Example 4-20 Context-Determined Expressions . . . . . . . . . . . . . . . . 4-21

Ex ample 5-1 Sequential Statements . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Example 5-2 Equivalent Comb inational Description . . . . . . . . . . . . 5-2

xxv

E xample 5-3 Combinational Ripple Carry Adder . . . . . . . . . . . . . . . 5-3

Example 5-4 Simple Function Decl aration . . . . . . . . . . . . . . . . . . . . 5-4

Example 5-5 Many Outputs From a Function. . . . . . . . . . . . . . . . . . 5-6

Ex ample 5-6 Register Declarations . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Example 5-7 Memory Declarat ions . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Example 5-8 Parameter Declaration in a Func tion. . . . . . . . . . . . . . 5-8

E xample 5-9 Integer Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Example 5-10 Procedural A ssignments . . . . . . . . . . . . . . . . . . . . . . . 5-11

Example 5-11 RTL Nonblocking Assignments . . . . . . . . . . . . . . . . . . 5-12

Example 5-12 Blocking Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Example 5-13 Block Statement With a Named Bloc k . . . . . . . . . . . . 5-14

Exam ple 5-14 if Statement That Synthesizes Multiplexer Logic. . . . . 5-16

Example 5-15 if...else if...else Structure. . . . . . . . . . . . . . . . . . . . . . . 5-17

Example 5-16 Nested if and else Statements . . . . . . . . . . . . . . . . . . 5-17

Example 5-17 Synthesizing a Latch for a Condit ionally Driven Variable

5-18

Example 5-18 case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

Example 5-19 A case Statement That Is Both Ful l and Parallel. . . . . 5-21

Example 5-20 A case Statement That Is Parallel but Not Full . . . . . . 5-22

Example 5-21 A case Statement That Is Not F ull or Parallel . . . . . . . 5-22

Ex ample 5-22 casex Statement With x . . . . . . . . . . . . . . . . . . . . . . . 5-23

Example 5-23 Before Using casex With ? . . . . . . . . . . . . . . . . . . . . . 5-24

Example 5-24 After Using casex With ?. . . . . . . . . . . . . . . . . . . . . . . 5-24

Example 5-25 Invalid casex Expression. . . . . . . . . . . . . . . . . . . . . . . 5-24

xxvi

Example 5-26 casez Statement With z . . . . . . . . . . . . . . . . . . . . . . . 5-26

Example 5-27 Invalid case z Expression. . . . . . . . . . . . . . . . . . . . . . . 5-26

Example 5-28 A Simple for Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

Example 5-29 Nested for Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Example 5-30 Example for Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Example 5-31 Expanded for Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Example 5-32 Unsupported while Loop . . . . . . . . . . . . . . . . . . . . . . . 5-29

Example 5-33 Supported while Loop . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

Example 5-34 Supported forever Loop . . . . . . . . . . . . . . . . . . . . . . . 5-30

Example 5-35 Comparator Using disable. . . . . . . . . . . . . . . . . . . . . . 5-31

Example 5-36 Synchronous Reset of State Regi ster Using disable in a

forever Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

Example 5-37 Using the task Statement . . . . . . . . . . . . . . . . . . . . . . 5-33

Example 5-38 A Simple always Block . . . . . . . . . . . . . . . . . . . . . . . . 5-34

Example 5-39 Incomplete Event List . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

Example 5-40 Complete Event List . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37

Example 5-41 Incomplete Event List for Asynch ronous Preload . . . . 5-37

Example 6-1 Inference Report for a JK Flip-Flop . . . . . . . . . . . . . . . 6-2

Example 6-2 SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Example 6-3 Inference Report for an SR Latch . . . . . . . . . . . . . . . . 6-8

Ex ample 6-4 Latch Inference Using an if Statement . . . . . . . . . . . . 6-10

Example 6-5 Latch Inference Using a case Statement . . . . . . . . . . 6-10

Example 6-6 Avoiding Latch Inference. . . . . . . . . . . . . . . . . . . . . . . 6-11

Example 6-7 Another Way to Avoid Latch Infere nce . . . . . . . . . . . . 6-11

xxvii

Example 6-8 Function: No Latch Inference . . . . . . . . . . . . . . . . . . . 6-11

Example 6-9 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Example 6-10 Inference Report for a D Latch . . . . . . . . . . . . . . . . . . 6-13

Example 6-11 D Latch With Asynchronous Set . . . . . . . . . . . . . . . . . 6-14

Example 6-12 Inference Report for D Latch With Asynchronous Set 6-14

Example 6-13 D Latch With Asynchronous Reset . . . . . . . . . . . . . . . 6-16

Example 6-14 Inference Report for D Latch With Asynchronous Reset

6-16

Example 6-15 D Latch With Asynchronous Set an d Reset . . . . . . . . 6-17

Example 6-16 Inference Report for D Latch With Asynchronous Set and Reset

6-18

Example 6-17 Invalid Use of a Conditionally Assigned Variable . . . . 6-19

Example 6-18 Two-Phase Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Example 6-19 Using an always Block to Infer a Flip-Flop . . . . . . . . . 6-21

Ex ample 6-20 Positive Edge-Triggered D Flip-Flop . . . . . . . . . . . . . . 6 -22

Example 6-21 Inference Report for a Positive Edge-Triggered D Flip-Flop

6-22

Example 6-22 Negative Edge-Triggered D Flip-Flop . . . . . . . . . . . . . 6 -23

Example 6-23 Inference Report for a Negative Edge-Triggered D Flip-Flop

6-23

Example 6-24 D Flip-Flop With Asynchronous Set . . . . . . . . . . . . . . 6 -24

Example 6-25 Inference Report for a D Flip-Flop With Asynchronous Set

6-25

Example 6-26 D Flip-Flop With A synchronous Reset . . . . . . . . . . . . 6-26

Example 6-27 Inference Report for a D Flip-Flo p With Asynchronous Reset

6-26

xxviii

Example 6-28 D Flip-Flop With Asynchronous Se t and Reset. . . . . . 6-27

Example 6-29 Inference Report for a D Flip-Flop With Asynchronous Set

and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Example 6-30 D Flip-Flop With Synchronous Set . . . . . . . . . . . . . . . 6-29

Ex ample 6-31 Inference Report for a D Flip-Flop With Synchronous Set

6-30

Example 6-32 D Flip-Flop With Synchronous Reset . . . . . . . . . . . . . 6-31

Example 6-33 Inference Report for a D Flip-Flop With Synchronous Reset

6- 31

Example 6-34 D Flip-Flop With Sync hronous and Asynchronous Load

6-32

Example 6-35 Inference Report fo r a D Flip-Flop With Synchronous and

Asynchronous Load . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

Example 6-36 Multiple Flip-Flops With Asynchronous and Synchronous Controls

6-34

Example 6-37 Inference Reports for Multiple Flip-Flops With

Asynchronous and Synchronous Controls . . . . . . . . . 6-34

Example 6-38 JK F lip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38

Example 6-39 Inference Report for JK Flip-Flop . . . . . . . . . . . . . . . . 6-38

Example 6-40 JK Flip-Flop With Asynchronous Se t and Reset . . . . . 6-40

Example 6- 41 Inference Report for JK Flip-Flop With Asynchronous Set

and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41

Example 6-42 Toggle Flip-Flop With Asynchrono us Set . . . . . . . . . . 6-42

Exam ple 6-43 Inference Report for a Toggle Flip-Flop With Asynchronous Set

6-42

Example 6-44 Toggle Flip-Flop With Asynchrono us Reset . . . . . . . . 6-43

xxix

Example 6-45 Inference Report: Toggle Flip-Flo p With Asynchronous Reset

6-44

Example 6-46 Toggle Flip-Flop With Enable a nd Asynchronous Reset6-45

Example 6- 47 Inference Report: Toggle Flip-Flop With Enable and

Asynchronous Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 6-45

Example 6-48 Circuit With Six Implied Registers. . . . . . . . . . . . . . . . 6-47

Example 6-49 Circuit With Three Imp lied Registers. . . . . . . . . . . . . . 6-48

Example 6-50 Delays in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

Example 6-51 Three-State Inference Report . . . . . . . . . . . . . . . . . . . 6-51

Example 6-52 Simple Three-State Driver. . . . . . . . . . . . . . . . . . . . . . 6-52

Example 6-53 Inference Report for Simple Three -State Driver . . . . . 6-53

Example 6-54 Inferring One Three-State Driver From a Single Block 6-54

Example 6-55 Single Block Inference Report. . . . . . . . . . . . . . . . . . . 6-54

Example 6-56 Inferring Three-State Drivers Fr om Separate Blocks . 6-56

Example 6- 57 Inference Report for Two Three-State Drivers. . . . . . . 6-56

Example 6-58 Three-State Driver With Register ed Enable . . . . . . . . 6-57

Exampl e 6-59 Inference Report for Three-State Driver With Registered Enable

6-58

Example 6-60 Three-State Driver Without Regi stered Enable. . . . . . 6-59

Example 6-61 Inference Report for Three-State Driver Without Registered Enable

6-59

Example 7-1 Four Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Example 7-2 Ripple Carry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Example 7-3 Carry-Lookahead Chain . . . . . . . . . . . . . . . . . . . . . . . 7-4

Example 7-4 4-Input Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

xxx

E xample 7-5 4-Input Adder With Parentheses . . . . . . . . . . . . . . . . . 7 -6

Example 7-6 Simple Arithmetic Ex pression . . . . . . . . . . . . . . . . . . . 7-8

Example 7-7 Parentheses in an Arithmetic Expre ssion . . . . . . . . . . 7-10

Exampl e 7-8 Adding Numbers of Different Bit-Widths . . . . . . . . . . . 7-11

Example 7-9 Simple Additions With a Common Subexpression . . . 7-13

Example 7- 10 Sharing Common Subexpressions . . . . . . . . . . . . . . . 7-13

Example 7-11 Unidentified Common Subexpression s . . . . . . . . . . . . 7-14

Exam ple 7-12 More Efficient Use of Operators . . . . . . . . . . . . . . . . . 7 -15

Example 7-13 A Simple Finite Stat e Machine . . . . . . . . . . . . . . . . . . 7-16

Example 7-14 Better Implementation of a Fini te State Machine . . . . 7-18

Exampl e 7-15 Summing Three Cycles of Data in the Implicit State Style (Prefe rred)

7-20

Example 7-16 Summing Three Cycles of Data in the Explicit State Style

(Not Advi sable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Example 7-17 Synchronous Reset—Explicit St ate Style (Preferred) . 7-22

Example 7-18 Synchronous Reset—Implicit State Style (Not Advisable)

7-23

Example 7-19 Inefficient Circuit Description With Six Implied Registers

7-24

Example 7-20 Circuit With Three Implied Regist ers. . . . . . . . . . . . . . 7-26

E xample 7-21 Mealy Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27

Example 7-22 Fully Sy nchronous Counter Design. . . . . . . . . . . . . . . 7-33

Example 7-23 Asynchronous Counter Design . . . . . . . . . . . . . . . . . . 7-33

Example 7-24 Equivalent Statements . . . . . . . . . . . . . . . . . . . . . . . . 7-35

Example 7-25 Inefficient Circuit Description W ith Two Array Indexes 7-36

xxxi

Example 7-26 Efficient Circuit Description Wi th One Array Index . . . 7-38

Example 8-1 // synopsys translate_on and // synopsys translate_off Directives

8-3

Example 8-2 // synopsys parallel_case Directiv es . . . . . . . . . . . . . . 8-4

Example 8-3 // synopsys full_case Directives . . . . . . . . . . . . . . . . . 8-6

Example 8-4 Latches and // synopsys full_case . . . . . . . . . . . . . . . 8-7

Example 8-5 // synopsys state_vector Example. . . . . . . . . . . . . . . . 8-9

Ex ample 8-6 Enumeration of Type Colors . . . . . . . . . . . . . . . . . . . . 8 -10

Example 8-7 Invalid enum Declar ation. . . . . . . . . . . . . . . . . . . . . . . 8-10

Example 8-8 More enum Type Declarations . . . . . . . . . . . . . . . . . . 8-11

Example 8-9 Invalid Bit Value Encoding for Colors . . . . . . . . . . . . . 8-11

Example 8-10 Enumeration Literals Used as Cons tants . . . . . . . . . . 8-11

Exam ple 8-11 Finite State Machine With // synopsys enum and // synopsys

state_vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

Example 8-12 Unsupported Bit-Select From Enum erated Type. . . . . 8-13

Example 8- 13 Unsupported Bit-Select (With Component Instantiation)

From Enumerated Type. . . . . . . . . . . . . . . . . . . . . . . . 8-13

Example 8-14 Using Inference With Enumerated Types . . . . . . . . . . 8-14

Example 8-15 Changing the Enumeration Enc oding . . . . . . . . . . . . . 8-14

Example 8-16 Supported Bit-Select From Enumerated Type. . . . . . . 8-15

Example 8-17 Enumerated Type Declar ation for a Port . . . . . . . . . . . 8-15

Example 8-18 Incorrect Enumerated Type Declar ation for a Port . . . 8-16

Example 8-19 Component Implication . . . . . . . . . . . . . . . . . . . . . . . . 8 -17

Example A-1 Count Zeros—Combin ational Version. . . . . . . . . . . . . A-3

Example A-2 Count Zeros—Sequential Version. . . . . . . . . . . . . . . . A-5

xxxii

Example A-3 Drink Machine—State Machine Vers ion . . . . . . . . . . . A-8

Example A-4 Drink Machine—Count Nickels Version. . . . . . . . . . . . A-10

Example A-5 Carry-Lookahead Adder . . . . . . . . . . . . . . . . . . . . . . . A-15

Example B-1 Valid Verilog Number Declarations . . . . . . . . . . . . . . . B-14

Ex ample B-2 Sample Escaped Identifiers . . . . . . . . . . . . . . . . . . . . B-15

Example B-3 Macro Variable Decl arations . . . . . . . . . . . . . . . . . . . . B-16

Example B-4 Macro With Sized Constants. . . . . . . . . . . . . . . . . . . . B-17

Example B-5 Including a File Within a File . . . . . . . . . . . . . . . . . . . . B-17

1-1

F PGA Compiler II / FPGA Express with Verilog HDL

FPGA Compiler II / FPGA Express with

Verilog HDL 1

FPGA Compiler II / FPGA Express translates and optimizes Verilog

HDL descriptions into an intern al gate-level equivalent, and then

compiles this representation to produc e optimized gate-level designs

in a given FPGA technology.

Th is chapter introduces the main concepts and capabilities of FPGA

Compiler II / FPGA

Express

in the following sections:

• Hardware Description Languages

• FPGA Compiler II / FPGA Express an d the Design Process

• Using FP GA Compiler II / FPGA Express to Compile a Verilog

HDL Design

• Design Methodology

1-2

F PGA Compiler II / FPGA Express with Verilog HDL

Hardware Description Languages

Hardware description languages (HDLs) describ e the architecture

and behavior of discrete electronic systems. Modern HDLs and their

associated simulators are very powerful tool s for integrated circuit

designers.

A typical HDL supports a mixed-level description in which gate and

netli st constructs are used with functional descriptions. This mixed-

level capability enables you to describe syst em architectures at a very

high leve l of abstraction and then incrementally refine a design’s

detailed gate-level implementation.

HDL descriptions play an important role in mo dern design

methodology, for three m ain reasons:

• Design functionality c an be verified early in the design process.

A design written as an HDL description can be simulated

immediately. Design simul ation at this higher level, before

i mplementation at the gate level, allows you to evaluate

architectural and design decisions.

• FPGA Compiler II / FPGA

Express provides Verilog compilation

and logic synthesis, allowing y ou to automatically convert an HDL

description to a gate-level implementati on in a target FPGA

technology . This step eliminates the former technology-specific

design bottleneck, the majority of circui t design time, and the

errors that occur when you hand-translate an HDL specification

to gates.

1-3

F PGA Compiler II / FPGA Express with Verilog HDL

With FPGA Compiler II / FPGA Express logic optimization, you

can automatically transform a synthesized desi gn into a smaller

or faster circuit. FPGA Compiler II / FPGA

Express provides both

logic synthesis and optimization. For furthe r information, refer to

FPGA Compile r II / FPGA

Express online help.

• HDL descriptions provide technology-indepe ndent

documentation of a design an d its functionality. An HDL

descrip tion is easier to read and understand than a netlist or a

schematic description. Because the initial HDL design description

is technology-in dependent, you can reuse it to generate the

design in a different technology, without havi ng to translate from

the original te chnology.

1-4

F PGA Compiler II / FPGA Express with Verilog HDL

FPGA Compiler II / FPGA Express and the Design

Process

FPGA Compiler II / FPGA

Express

translates hardware descriptions

in Verilog to a Synopsys internal design forma t. The design can then

be optimized and mapped to a specific FPGA technology library by

FPGA Compiler II / FPGA

Express , as Figure 1-1 shows.

Figure 1-1 FPGA Compiler II / FPGA Exp ress Design Process

FPGA Compile r II / FPGA Express supports a majority of the Verilo g

constructs. (For excepti ons, see “Unsupported Verilog Language

Constructs” on page B-20.)

Verilog

Description

FPGA Compiler II /

Optimized

Technology-Specific

Netlist

FPGA Technology Library FPGA

Express

1-5

F PGA Compiler II / FPGA Express with Verilog HDL

Using FPGA Compiler II / FPGA Express to Compile a

Verilog HDL Design

When a Verilog design is read into FPGA Comp iler II / FPGA

Express

it is converted to an internal database format so FPGA Compiler II /

FPGA

Express

can synthesize and optimize the design. When FPGA

Compiler II / FPGA

Express optimizes a design, it may restru cture

part or all of the design . You control the degree of restructuring.

Options include:

• Fully preserving a design’s hierarchy

• Allowing certain modules to b e combined with others

• Compr essing the entire design into one module (called flattening

the design), if that is beneficial

The following section describes the design process that uses FPGA

Compiler II / FPGA

Express with a Verilog HDL Simulator.

1-6

F PGA Compiler II / FPGA Express with Verilog HDL

Design Methodology

Figure 1-2 shows a typical design process that uses FPGA Compiler

II / FPGA

Express and a Verilog HDL Simulator.

Figure 1-2 Design Flow

Verilog

Synopsys

FPGA Compiler II /

Verilog HDL

Simulation Output

Compare

Output

Verilog HDL

Test Driver

Verilog HDL

FPGA Vendor

Development System

FPGA

Express

Simulation Output

Description

SimulatorSimulator

1-7

F PGA Compiler II / FPGA Express with Verilog HDL

The steps in the design flow shown in Fi gure 1-2 are:

1. Write a design description in the Verilog language. This

description can be a combination of stru ctural and functional

elements (as shown in Chapter 2, "Description Styles”). This

description is for use with both Synops ys FPGA Compiler II /

FPGA

Express and a Verilog simulator.

2. Provide Verilog-language test driv ers for the Verilog HDL

simula tor. For information on writing these drivers, see the

appropriate simulator manual. The driver s supply test vectors for

simul ation and gather output data.

3. Simulate the design by using a Verilog HDL simulator. Verify that

the description is correct.

4. Use FPGA Compiler II / FPGA

Express to synthesize and optimize

the Verilog description into a gate-level design. FPGA Compiler

II / FPGA

Express generates optimized netlists to satisfy timing

constraints for a targeted FPGA architecture.

5. Use your FPGA development system to place and route the FPGA

netlist. Then generate a Verilog netlist for post-place-and-route

simula tion. The development system includes simulation models

and interfaces required for the design fl ow.

6. Simulate the technology- specific version of the design with the

Verilog simulator. You can use the origin al Verilog simulation

driver s from step 3 because module and port definitions are

preserved through the translation and opt imization processes.

7. Compar e the output of the gate-level simulation (step 6) with the

output of the original Verilog descripti on simulation (step 3) to

veri fy that the implementation is correct.

1-8

F PGA Compiler II / FPGA Express with Verilog HDL

2-1

Description Styles

Description Styles 2

A Verilog circuit description can be on e of two types: structural or

functional. A structural description explains the physical makeup of

the circuit, detailing gates and the connections between them. A

fun ctional description

, also referred to as an RTL (Regis ter Transfer

Level) description , describes what the circuit does.

This chapter covers the following topics:

• Design Hierarchy

• Structural Descriptions

• Functional Descriptions

• Mixing Structural and Functional Descri ptions

• Register Selection

• Asynchronous Designs

2-2

Description Styles

Design Hierar chy

Synopsys FPGA Compiler II / FPGA

Express

maintains the

hierarchical boundaries you define when you us e structural Verilog.

These boundari es have two major effects:

• Con straints can be specified on a per-module basis. For example,

this allows some modules to be optimized for area while others

are optimized fo r speed.

• Module instantiations wit hin HDL descriptions are maintained

during input. The instance name you assign to user-defined

components is carried through to the gate-lev el implementation.

Chapter 3, "Struc tural Descriptions”, discusses modules and module

instantiations.

Note:

FPGA Compiler II / FPGA

Express does not automatically

maintain (create) the hierarchy of other, nonstructural Verilog

constr ucts such as blocks, loops, functions, and tasks. These

elements of an HDL description are transl ated in the context of

their de sign.

The choice of hierarchic al boundaries has a significant effect on the

quality of the synthesized design. Using FPGA Compiler II / FPGA

Expr ess, you can optimize a design whi le preserving these

hierarchic al boundaries. However, FPGA Compiler II / FPGA

Express

only partially optimizes logic across hie rarchical modules. Full

optimi zation is possible across those parts of the design hierarchy

that are collapsed in FPGA Compiler II / FPGA

Express

2-3

Description Styles

Structural De scriptions

The structural elements of a Verilog structural description are generic

logic gates, library-specific components, an d user-defined

components connected by wires. In one way, a structural description

can be viewed as a simple netlist composed of nets that connect

instantiations of gates. However, unlike in a netlist, nets in the

structural description can be driven by an ar bitrary expression that

describes t he value assigned to the net. A statement that drives an

arbitrary expression onto a net is called a co ntinuous assignment.

Continuous assi gnments are convenient links between pure netlist

descriptions and functional descriptions.

A Verilog structural description can define a range of hierarchical and

gate-level constructs, including module definitions, module

instantiations, and netlist connections. Refer to Chapter 3, "Structural

Descripti ons”, for more information.

Fu nctional Descriptions

The functional elements of a Verilog description are function

declarations, task statements, and always bloc ks. These elements

describe the func tion of the circuit but do not describe its physical

makeup or layout. The choice of gates and comp onents is left entirely

to FPGA Comp iler II / FPGA

Express .

You can construct functional descriptions wit h the Verilog functional

constr ucts described in Chapter 5, "Functional Descriptions”. These

constructs can appear within functions or alwa ys blocks. Functions

imply only comb inational logic; always blocks can imply either

combinational or sequential logic.

2-4

Description Styles

Although many Veri log functional constructs (for example, for loops

and multiple assignments to the same variable) appear sequential in

nature, they describe combinational-logic networks. Other functional

constructs imply sequential-logic networks. La tches and registers are

inferred fro m these constructs. Refer to Chapter 6, "Register and

Three-State Inference” for details.

Mixing Structural and Functional Desc riptions

When you use a functional de scription style in a design, you typically

describe the combinational portions of the de sign in Verilog functions,

always bl ocks, and assignments. The complexity of the logic

determines whether you use one or many functio ns.

Example 2-1 shows how structural and functional description styles

a re mixed in a design specification. In Example 2-1, the function

detect_logic determines whether the input bit is a 0 or a 1. After

making this de termination, detect_logic sets ns to the next state of

the machine. An always block infers flip-flops to hold the state

information betwe en clock cycles.

You can specify elem ents of a design directly as module instantiations

at the structural level. For example, see th e three-state buffer t1 in

Example 2-1. (Note that three-states can be inferred. For more

information, refer to “Three-State Inference” on page 6-51.) You can

also use thi s description style to identify the wires and ports that carry

information from one part of the design to ano ther.

2-5

Description Styles

Example 2-1 Mixed Structural and Functional Descriptions

// This finite-state m achine (Mealy type) reads one bit per

// clock cycle and detects three or more consecutive 1s.

module three_ones( sig nal, clock, detect, output_enable );

input signal, clock, output_enable;

output detect;

// Declare current sta te and next state variables.

reg [1:0] cs;

reg [1:0] ns;

wire ungated_detect;

// declare the symbolic names for states

parameter NO_ONES = 0, ONE_ONE = 1,

TWO_ONES = 2, AT_LEAST_THREE_ONES = 3;

// ************* STRUC TURAL DESCRIPTION ****************

// Instance of a three-state gate that enables output

three_state t1 (ungate d_detect, output_enable, detect);

// ******************* ALWAYS BLOCK ********************

// always block infers flip-flops to hold the state of

// the FSM.

always @ ( posedge clo ck ) begin

cs <= ns;

end

// ************* FUNCTIONAL DESCRIPTION ****************

function detect_logic;

input [1:0] cs;

input signal;

begin

detect_logic = 0; //default value

if ( signal == 0 ) //bit is zero

ns = NO_ONES;

else //bit is one, increment state

case (cs)

NO_ONES: ns = ONE_ONE;

ONE_ONE: ns = TWO_ONES;

TWO_ON ES, AT_LEAST_THREE_ONES:

begin

ns = AT_LEAST_THREE_ONES;

detect_logic = 1;

end

endcase

end

endfunction

2-6

Description Styles

// ************** assign STATEMENT **************

assign ungated_detect = detect_logic( cs, signal );

endmodule

For a structural or functional HDL description to be synthesized, it

m ust follow the Synopsys synthesis policy, which has three parts:

• Design Methodology

• Description Style

• Language Constructs

Design Methodology

Design methodology refers to the synthesis de sign process that uses

FPGA Compiler II / FPGA

Express and Verilog HDL Simulator. This

process is described in Chapter 1, "FPGA Compiler II / FPGA Express

with Verilog HDL”.

Description Style

Use the HDL design and coding style that make s the best use of the

synthesis proc ess to obtain high-quality results from FPGA Compiler

II / FPGA

Express

. See Chapter 7, "Writing Circuit Description s”, for

guidelines.

Language Constructs

The third component of the Verilog synthesis p olicy is the set of Verilog

constr ucts that describe your design, determine its architecture, and

give consistently good results.

2-7

Description Styles

Synopsys uses HDL constructs that maximize coding flexibility while

producing consistently good results. Although FPGA Compiler II /

FPGA

Express can read the entire Verilog langu age, a few HDL

constructs canno t be synthesized. These constructs are unsupported

because they cannot be realized in logic. For example, you cannot

use simulation time as a trigger because time is an element of the

simulation process and cannot be realized . “Unsupported Verilog

Languag e Constructs” on page B-20 lists these constructs.

The clocking scheme and the placement of regi sters are important

architectural factors. There are two ways to d efine registers in your

Verilog de scription. Each method has specific advantages.

• You can directly instantiate registers into a Verilog description,

selecting fr om any element in your FPGA library.

Clocking schemes can be arbitrarily complex. Y ou can choose

between a flip-flop an d a latch-based architecture. The main

disadvantages to this approach are that

- The Verilog description is specific to a given technology,

because you choo se structural elements from that technology

library. However, you can isolate the portion of your design with

directly instan tiated registers as a separate component

(module), and then connect it to the rest of t he design.

- The description is more difficult to write.

2-8

Description Styles

• You can use some Verilog constructs to dire ct FPGA Compiler II

/ FPGA

Express to infer registers from the descriptio n.

The advantages to this approach d irectly counter the

disadvantages of the previous approach. With register inference,

the Verilog description is much easier to wr ite and is technology-

independent. T his method allows FPGA Compiler II / FPGA

Express

to select the type of component inferred, ba sed on

constraints. Therefore, if a specific component is necessary, use

instantiation. Some types of registers and la tches cannot be

inferred.

See “Register Inference” on page 6-1 for a di scussion of latch and

Asynchronous Designs

You can use FPGA Compiler II / FPGA Express to construct

asynchronous designs that use multiple or gate d clocks. However,

although these de signs are logically and statically correct, they may

not simulate or operate correctly because of r ace conditions.

“Synthesis Issues” on page 7-31 describes how to write Verilog

descriptions of asynchronous designs.

3-1

S tructural Descriptions

Structural Descriptions 3

A Verilog structural description defines a connection of components

that form a physical circuit. This chapter details the construction of

structural descriptions, in the following major sections:

• Modules

• Macromodules

• Port Definitions

• Module Statements and Constructs

• Module Instantiations

3-2

Structural Descriptions

Modules

The principal design entity in the V erilog language is the module. A

mod ule consists of the module name, its input and output description

(port definition), a description of the func tionality or implementation

for th e module (module statements and constructs), and named

instantiations. Figure 3-1 illustrates the ba sic structural parts of a

module.

Figure 3-1 Structural Parts of a Module

Example 3-1 shows a si mple module that implements a 2-input NAND

gate by instantiating an AND gate and an INV gate. The first line of

the module definition gives the name of the module and a list of ports.

The second and third lines give the di rection for all ports. (Ports are

either inputs, outputs, or bidirectionals .)

Module

Definitions:

Port, Wire, Register,

Parameter, Integer,

Function

Module Statements

and Constructs Module Instantiations

Module Name

and Port List

3-3

S tructural Descriptions

The fourth lin e of the description creates a wire variable. The next

two lines instantiate the two components, crea ting copies named

instance1 and inst ance2 of the components AND and INV. These

components connect to the ports of the module and are finally

connected by use of the variable and_out.

Example 3-1 Module Definition

module NAND(a,b,z);

input a,b; //Inputs to NAND gate

output z; //O utputs from NAND gate

wire and_out; //Output from AND gate

AND instance1(a,b,and_out);

INV instance2(and_out, z);

endmodule

Macromodules

The macromodule construct makes simulation mo re efficient, by

merging the macromo dule definition with the definition of the calling

(parent) module. However, FPGA Compiler II / F PGA

Express treats

the macromodule construct as a module constr uct. Whether you use

module or macr omodule, the synthesis process, the hierarchy

synthesis creates, and its result are the sa me. Example 3-2 shows

how to use th e macromodule construct.

Example 3-2 Macromodule Construct

macromodule adder (in1,in2,out1);

input [3:0] in1,in2;

output [4:0] out1;

assign out1 = in1 + in2;

endmodule

3-4

Structural Descriptions

Note:

When FPGA Compiler II / FPGA

Express

instantiates a

macromodule, a new level of hierarchy is created.

Port Definitions

A port list consists of port express ions that describe the input and

ou tput interfaces for a module. Define the port list in parentheses after

the module name, as shown here:

module name ( port_list );

A port expression in a port list can be any of the following:

• An identifier

• A single bit selected from a bit v ector declared within the module

• A group of bits selected from a bit vector declared within the

module

• A concatenation of any of the above

Concatenation is the process of combining s everal single-bit or

multiple-bit o perands into one large bit vector. For more information,

see “Concatenation Operators” on page 4-13.

Declare each port in a port list as input, output, or bidirectional in the

module by use of an input, output, or inout statement. (See “Port

Declarations” on page 3-14.) For example, the module definition in

Example 3-1 on page 3-3 shows that module NAND has three ports:

a, b, and z, conne cted to 1-bit nets a, b, and z. Declare these

connections in the input and output statements .

3-5

S tructural Descriptions

Port Names

Some port expressions are id entifiers. If the port expression is an

identifier, the port name is the same as the i dentifier. A port expression

is no t an identifier if the expression is a single bit, a group of bits

selected from a vector of bits, or a concaten ation of signals. In these

cases, th e port is unnamed unless you explicitly name it.

Example 3-3 shows some module definition frag ments that illustrate

the use of por t names. The ports for module ex1, named a, b, and z,

are connected to nets a, b, and z, respectivel y. The first two ports of

module ex 2 are unnamed; the third port is named z. The ports are

connected to nets a[1], a[0], and z, respectiv ely. Module ex3 has two

ports: the first port, unnamed, is connected t o a concatenation of nets

a and b; the second port, named z, is connected to net z.

Example 3-3 Module Port Lists

module ex1( a, b, z );

input a, b;

output z;

endmodule

module ex2( a[1], a[0], z );

input [1:0] a;

output z;

endmodule

module ex3( {a,b}, z );

input a,b;

output z;

endmodule

3-6

Structural Descriptions

Renami ng Ports

You can rename a port by exp licitly assigning a name to a port

e xpression by using the dot (.) operator. The module definition

fragments in Example 3-4 show how to rename po rts. The ports for

module ex4 are ex plicitly named in_a, in_b, and out and are

connected to nets a, b, and z. Module ex5 shows ports named i1, i0,

and z connected to nets a[1], a[0], and z, re spectively. The first port

for modul e ex6 (the concatenation of nets a and b) is named i.

Example 3-4 Renaming Ports in Modules

module ex4( .in_a(a), .in_b(b), .out(z) );

input a, b;

output z;

endmodule

module ex5( .i1(a[1]), .i0(a[0]), z );

input [1:0] a;

output z;

endmodule

module ex6( .i({a,b}), z );

input a,b;

output z;

endmodule

3-7

S tructural Descriptions

Modul e Statements and Constructs

FPGA Comp iler II / FPGA

Express

recognizes the following Verilog

statements and constructs when they are used i n a Verilog module:

• parameter decl arations

• wire, wand, wor, tri, supply0, and supply1 declarat ions

• reg declarations

• input declarations

• output declarations

• inout declarations

• Continuous assignments

• Module instantiations

• Gate instantiations

• Function definitions

• always blocks

• task statements

Data declarations and assignments are describe d in this section.

Module and gate i nstantiations are described in “Module

Instantiations” on page 3-17. Function defini tions, always blocks, and

task stat ements are described in Chapter 5, "Functional

Descriptions”.

3-8

Structural Descriptions

Structural Data Types

Verilog struct ural data types include wire, wand, wor, tri, supply0, and

supply1. Although parameter does not fall in to the category of

structural data types, it is presented here because it is used with

structural data types.

You can define an optional range for all the d ata types presented in

this section. The range provides a means for creating a bit vector.

The syntax for a range specification is

[msb : lsb]

Expressions for most significant bit (msb) a nd least significant bit (lsb)

must be nonnegative constant-valued expressions. Constant-valued

expressions are composed only of constants, Ve rilog parameters,

and operators.

parameter

Verilog parameters allow you to customize ea ch instantiation of a

module. By setting different values for the parameter when you

instantiate the module, you can cause construc tions of different logic.

For more i nformation, see “Parameterized Designs” on page 3-19.

A parameter represents constant values symboli cally. The definition

for a paramet er consists of the parameter name and the value

assigned to it. The value can be any constant- valued integer or

Boolean expression . If you do not set the size of the parameter with

a range definition or a sized constant, the pa rameter is unsized and

defaul ts to a 32-bit quantity. Refer to “Constant-Valued Expressions”

on page 4-2 for a discussion of constant form ats.

3-9

S tructural Descriptions

You can us e a parameter wherever a number is allowed, e