MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 1)
A CSM centered view of the Front-End
J. Chapman - February 2001
CSM Interactions with ASD/TDC/TTC/DCS/MROD
Tubes
Hedgehog
Mezzanine
40
TTCrx
MROD
106.7 Mbyte/s
S-Link/G-Link
TTC
TTC Fibre
Clk, L1A, Calib
Mux
JTAG
Monitor
ELMB
Mux
18 Mezzanine
Cards Maximum
64 ADCs
ELMB
CAN
Bus
ROB
To
TTCvi
Central
Control
CSM
Copper JTAG
Serial to Parallel
Xtmr
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 2)
Calibration via TTC System
Provisions in TTC system
- B channel commands provide for calibration - addressable by TTC/CSM.
- Can use the second TTC clock phase to give 104ps fine edge timing.
- Can use Inhibit(0-3) (position in orbit to pulse) for course timing.
- The TTC system has 4 triggers(0-3), one L1A from CTP and others for test.
Sequence for test pulsing
TTCvi
Set
orbit
pulse
time
N ticks
TTCrx
CSM
ASD
f 2
Setup data
for pulse on
MROD to CSM
delay
L1A
synchronized pulse
pulse
JTAG
setup
Mk II
JTAG lines
MROD
Crossing
f 1
L1A
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 3)
Timing Calibration at the ASD (John Oliver)
Amplitude Decode
Dummy
switches
(masked off)
Bits[0:2]
Mask
50fF
STR
STR
LVDS
Levels
ASD
Calibration Injection
Qin = 0,...,8 x 10 fC
= 0,....80 fC
Q
threshold
= 5 fC
Calibration pulse time constant ~ 0.1ns (to 20%) i.e. Delayless
Note: Must hide return edge of calibration pulse or place it out of time
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 4)
Signal Counts
Mezzanine to CSM Motherboard x 18 max
- 8 JTAG (LVDS), 8 Data/CLK (LVDS) = 16 lines
- 8 Analog PWR, 8 Digital PWR, 6 Sense, 2 Calibration = lines
CSM to CSM Motherboard - 3 x 140 pins = 420 pins
- 8 JTAG (LVDS), 10 Data/CLK (LVDS) x 18 mezzanine cards = 324 lines
- 6 Sense, 8 Digital PWR, 8 ELMB PWR = lines
ELMB Mux to CSM Motherboard
- 6 Sense x 18 Mezzanine cards, 6 Sense x 1 CSM = 114 lines
- 8 Digital I/O, 10 ELMB SPI = lines
Conclusion - it works with spare pins ( dense with traces! )
2416 + 40 =
22324 + 346=
18114 + 132
=
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 5)
G-Link Test Fixtures
G-Link encoder chip (HDMP-1032 & HDMP-1034)
Optical transceiver Infineon (V23818K305V17)
Xilinx Virtex XCV50E-FG256C (capable of LVDS I/O)
4 volt to 3.3 volt regulator (as used on Mezzanine card)
4 volt to 2.5 volt & 1.8 volt with same series regulators
Virtex
FPGA
40MHz
LVDS
Clock
HDMP
1032
HDMP
1034
Infineon
transmitter
Infineon
receiver
Pattern Generator
53.3MHz
17 bits
External
Copy of
Pattern Tester
JTAG
Setup
To/from
the same
circuit
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 6)
Whats Different from the Prototype?
Existing CSM-0 Module FIFO
3 28mm FPGAs
G-Link/S-Link to MROD
2 17mm FPGAs
1 40mm FPGA 1 17mm FPGA
1 28mm FPGA 1 10mm TTCrx
115 x 166mm board 80 x 130mm
+ receiver
LVDS on VME LVDS FPGA
Event Building Time Division Mux
Clock Fanout In FPGA DLL
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 7)
CSM-0 Connections
Tubes
Hedgehog
Mezzanine
40
TTCem
Mux
JTAG
18 Mezzanine
Cards Maximum
CSM-0
Serial to Parallel
FIFO
VME
Interface
PC
A
d
a
p
t
e
r
4
0
p
i
n
t
o
R
J
4
5
Power
Trigger/Clock
MDT Electronics PDR February 22, 2001
May 1, 2001 - J. Wehrley Chapman (Page 8)
List of Initial Jobs
Study documents (after copying) to get overview of system.
Capture all windows in MiniDaq for update of manual.
Test, diagnose, & repair CSM-0 cards that need certification.
Count all signal pins for FPGA designs to estimate package.
Study VHDL code for S-Link to build core for FPGA.
Setup MiniDaq system with 4 Mezzanine cards & trigger.
Work with chamber (gas & HV) & scintillator cosmic trigger.
Do Verilog simulation tests of clock phase selector.