`timescale 1ns/1ns

module ttcem(clk25, reset, addr, data, chip_sel_b, read_writeb, dbe0,
             trigger_in, ff_almost_full_b, ff_almost_empty_b,
             evid, bcid, version, l1_del_trig, tdc_command_data,
             stop);
//             , extra_io2, extra_io3, extra_io4);

input clk25, reset, chip_sel_b, read_writeb, dbe0, trigger_in, 
      ff_almost_full_b, ff_almost_empty_b;
input [2:0] addr;
input stop;
//, extra_io2, extra_io3, extra_io4;
inout [31:0] data;

output [11:0] evid, bcid, version;
output l1_del_trig, tdc_command_data;

  reg [31:0] data_in_latched;
  reg [31:0] csr;
  reg [11:0] bcid_rollover, bcid_latch;
  reg [6:0] l1_pipe_length;
  reg [6:0] delay_pipe;
  reg ff_fill_en;
  reg l1_del_trig;

  wire [11:0] evid, bcid;
  wire csr_sel, l1_pipe_length_sel, bcid_rollover_sel, evid_sel,
       bcid_sel, ec_preset_sel, bc_preset_sel, delay_pipe_sel;
  wire [31:0] data_bus;
  wire one_dbe0;
  wire bc_preset_delay, ec_preset_delay, gl_reset_delay;
  wire l1_trig_qual2;

//  Set to version 2 1/27/00.  First really working version, other than 
//      just registers.

//  parameter [11:0] VERSION = 12'd1; // UPDATE THIS AS NECESSARY
  parameter VERSION = 12'd5; // UPDATE THIS AS NECESSARY
  wire [11:0] version;
  assign version = VERSION;

  supply1 Vdd;
  supply0 GND;

/*
  addr 0 -> csr (read/write)
  addr 1 -> l1 pipe length (read/write)
  addr 2 -> bcid_rollover value (read/write)
  addr 3 -> evid (read) 
  addr 4 -> bcid (read)
  addr 5 -> ec_preset value (read/write)
  addr 6 -> bc_preset value (read/write)
  addr 7 -> Delay pipe length for ec and bc presets and gl reset
*/

  assign #1 csr_sel = 
	    ~addr[2] & ~addr[1] & ~addr[0] & ~chip_sel_b; // address 0
  assign #1 l1_pipe_length_sel = 
            ~addr[2] & ~addr[1] & addr[0] & ~chip_sel_b; // address 1
  assign #1 bcid_rollover_sel = 
            ~addr[2] & addr[1] & ~addr[0] & ~chip_sel_b; // address 2
  assign #1 evid_sel = 
            ~addr[2] &  addr[1] & addr[0] & ~chip_sel_b; // address 3
  assign #1 bcid_sel = 
            addr[2] & ~addr[1] & ~addr[0] & ~chip_sel_b; // address 4
  assign #1 ec_preset_sel = 
            addr[2] & ~addr[1] & addr[0] & ~chip_sel_b; // address 5
  assign #1 bc_preset_sel = 
            addr[2] & addr[1] & ~addr[0] & ~chip_sel_b; // address 6
  assign #1 delay_pipe_sel =
            addr[2] & addr[1] & addr[0] & ~chip_sel_b; // address 7

  wire trig_en, soft_trig, bc_preset_bit, ec_preset_bit, global_reset;

// Excess csr bits are latched but not used (useful for readback)
  assign trig_en = csr[0];
  assign soft_trig = csr[1];
  assign global_reset = csr[2];
  assign bc_preset_bit = csr[3];
  assign ec_preset_bit = csr[4];

// code to put chip's data_bus data onto output pins (reads)

  assign #1 data = (read_writeb && ~chip_sel_b && ~dbe0) ? data_bus : 32'bZ;

// input data latch as suggested by Xilinx for synthesis (writes)

  always @(read_writeb or chip_sel_b or data or dbe0) begin
    if (~read_writeb && ~chip_sel_b && ~dbe0) data_in_latched <= #1 data;
  end

// put latched input data onto chip's data_bus

  assign #1 data_bus = (~read_writeb && ~chip_sel_b && ~dbe0) ?
                         data_in_latched : 32'bZ;

// clock data into various registers

  always @(posedge clk25) begin
    if (reset) begin
	csr <= #1 5'b00000;
    end
    else begin
	if (csr_sel && ~read_writeb && ~dbe0) csr <= #1 data_in_latched;
    end
  end

  always @(posedge clk25) begin
    if (l1_pipe_length_sel && ~read_writeb && ~dbe0) l1_pipe_length <= #1 data_in_latched[6:0];
  end

  always @(posedge clk25) begin
    if (bcid_rollover_sel && ~read_writeb && ~dbe0) bcid_rollover <= #1 data_in_latched[11:0];
  end
  
  always @(posedge clk25) begin
    if (delay_pipe_sel && ~read_writeb && ~dbe0) delay_pipe <= #1 data_in_latched[6:0];
  end

// enable various data sources onto chip's data_bus.  Always prepare the
// current bcid for output in case that is what is being requested.

  one_pulse dbe0_onepulse(clk25, reset, ~dbe0, one_dbe0);
  always @(posedge one_dbe0) begin
    bcid_latch <= #1 bcid;
  end

  assign #1 data_bus = (csr_sel && read_writeb) ? csr : 32'bZ;
  assign #1 data_bus = (l1_pipe_length_sel && read_writeb) ? 
  	{25'b0000000000000000000000000, l1_pipe_length} : 32'bZ;
  assign #1 data_bus = (bcid_rollover_sel && read_writeb) ? 
  	{20'b00000000000000000000, bcid_rollover} : 32'bZ;
  assign #1 data_bus = (evid_sel && read_writeb) ? 
  	{20'b00000000000000000000, evid} : 32'bZ;
  assign #1 data_bus = (bcid_sel && read_writeb) ? 
  	{20'b00000000000000000000, bcid_latch} : 32'bZ;
  assign #1 data_bus = (delay_pipe_sel && read_writeb) ? 
  	{25'b0000000000000000000000000, delay_pipe} : 32'bZ;
    
  control_pipe  bc_pipe(clk25, reset, bc_preset_pulse, bc_preset_delay, delay_pipe),
  		ec_pipe(clk25, reset, ec_preset_pulse, ec_preset_delay, delay_pipe),
  		gl_pipe(clk25, reset, global_reset_pulse, gl_reset_delay, delay_pipe);
  		
  one_pulse soft_trig_onepulse(clk25, reset, soft_trig, soft_trig_pulse),
            bc_preset_onepulse(clk25, reset, bc_preset_bit, bc_preset_pulse),
            ec_preset_onepulse(clk25, reset, ec_preset_bit, ec_preset_pulse),
            global_reset_onepulse(clk25, reset, global_reset, global_reset_pulse);

/*
 *  Triggers coming from the external pin, or from the soft trigger, cause
 *  a cascade of signals internally.  For the external trigger, these are:
 *   trigger_in       -> signal entering chip
 *   l1_trigger_qual  -> latched trigger, synced with clk25 and at least
 *                      one clock long.
 *   l1_trig_qual2    -> latch again to protect against asynch timing violations
 *   l1_trigger       -> masked, qualified trigger which enters pipe.
 *   l1_del_trig_qual -> trigger emerging from pipeline.
 *   l1_del_trig      -> trigger out of chip, if tdc_cmnd is not busy
 */

// Note: to use one_pulse requires trigger_in >= 25ns high

//  trigger_latch trigger_latch1(clk25, reset, trigger_in, l1_trigger_qual);
  one_pulse trigger_latch1 (clk25, reset, trigger_in, l1_trigger_qual),
  	    trigg_latch2 (clk25, reset, l1_trigger_qual, l1_trig_qual2);
 
  always @(posedge clk25) begin
      if (reset) begin
        ff_fill_en <= #1 1;
      end
      else begin
        if (~ff_almost_full_b) ff_fill_en <= #1 0;
        if (~ff_almost_empty_b) ff_fill_en <= #1 1;
	if (stop) ff_fill_en <= #1 0;
      end
  end

  wire l1_trigger, tdc_comm_busy, l1_del_trig_qual, trig_busy;
  assign #1 l1_trigger = ~trig_busy & (soft_trig_pulse | 
                         (ff_fill_en & trig_en & l1_trig_qual2));

  l1_trig_pipe l1_trig_pipe1(clk25, reset, l1_trigger,
                             l1_pipe_length, l1_del_trig_qual);

  trigger_mask_fsm trig_mask(clk25, reset, l1_trigger, trig_busy);
  
//  l1_del_trig <= #1 (~tdc_comm_busy) ? l1_del_trig_qual : 0;
  always @(posedge clk25) begin
	if (~tdc_comm_busy) begin
	    l1_del_trig <= #1 l1_del_trig_qual;
	end
	else begin
	    l1_del_trig <= #1 0;
	end
  end

  evid_counter evid_counter1(clk25, reset, ec_preset_sel, read_writeb,
                             dbe0, ec_preset_delay,
                             gl_reset_delay, data_bus, 
                             l1_del_trig, evid);


  bcid_counter bcid_counter1(clk25, reset, bc_preset_sel, read_writeb,
                             dbe0, bc_preset_delay, gl_reset_delay,
                             data_bus, bcid_rollover, bcid);  

  tdc_comm_fsm tdc_comm_fsm1(clk25, reset, l1_del_trig, bc_preset_pulse,
                             ec_preset_pulse, global_reset_pulse, 
                             tdc_command_data, tdc_comm_busy);

STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule











`timescale 1ns/100ps

module bcid_counter(clk25, reset, select, read_writeb, dbe0, 
                    preset_pulse, global_reset_pulse, 
                    data_bus, rollover, bcid);

input clk25, reset, preset_pulse, global_reset_pulse;
input select, read_writeb, dbe0;
input [11:0] rollover;
inout [31:0] data_bus;
output [11:0] bcid;

reg [11:0] bcid, preset;
reg [2:0] curr_state;

parameter       RESET =      3'b000,
                PRESET =     3'b010,
                INCREMENT =  3'b100;

// preset write code

always @(posedge clk25) begin
   if (select && ~read_writeb && ~dbe0) preset <= #1 data_bus[11:0];
end

// preset read code

assign #1 data_bus = (select && read_writeb && ~dbe0) ? 
                     {20'b0, preset} : 32'bZ;

always @(posedge clk25) begin
  if (reset) 				bcid <= #1 0;
  else if (curr_state == RESET) 	bcid <= #1 0;
  else if (curr_state == PRESET) 	bcid <= #1 preset;
  else if (bcid >= rollover) 		bcid <= #1 0;
  else 					bcid <= #1 bcid+1;
end
  
always @(posedge clk25) begin  

    if (reset) 				curr_state <= #1 RESET;
    
    if (curr_state == RESET) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (preset_pulse) 		curr_state <= #1 PRESET;
      else 				curr_state <= #1 INCREMENT;
    end

    else if (curr_state == PRESET) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else 				curr_state <= #1 INCREMENT;      
    end

    else if (curr_state == INCREMENT) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (preset_pulse) 		curr_state <= #1 PRESET;
      else 				curr_state <= #1 INCREMENT;
    end

end

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule





`timescale 1ns/100ps

module control_pipe(clk25, reset, in, out, pipe_length);

input clk25, reset, in;
input [6:0] pipe_length;
output out;

// Delay modules appear in l1_trig_pipe.v

delay_64_stage   control64(clk25, reset, pipe_length[6], in,         del64_out);
delay_32_stage   control32(clk25, reset, pipe_length[5], del64_out,  del32_out);
delay_16_stage   control16(clk25, reset, pipe_length[4], del32_out,  del16_out);
delay_8_stage     control8(clk25, reset, pipe_length[3], del16_out,  del8_out);
delay_4_stage     control4(clk25, reset, pipe_length[2], del8_out,   del4_out);
delay_2_stage     control2(clk25, reset, pipe_length[1], del4_out,   del2_out);
delay_1_stage     control1(clk25, reset, pipe_length[0], del2_out,   out);

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule
`timescale 1ns/100ps

module evid_counter(clk25, reset, select, read_writeb, dbe0, 
                    preset_pulse, global_reset_pulse,
                    data_bus, trigger, evid);

input clk25, reset, preset_pulse, global_reset_pulse;
input dbe0, select, trigger, read_writeb;
inout [31:0] data_bus;
output [11:0] evid;
reg [3:0] curr_state;
reg [11:0] preset;
reg [11:0] evid;

parameter       RESET =       4'b0000,
                PRESET =      4'b0010,
                WAITING =     4'b0100,
                INCREMENT =   4'b1000;
 
// preset write code

always @(posedge clk25) begin
   if (select && ~read_writeb && ~dbe0) preset <= #5 data_bus[11:0];
end

// preset read code

assign #5 data_bus = (select && read_writeb && ~dbe0) ? 
                     {20'b0, preset} : 32'bZ;

always @(posedge clk25) begin
  if (reset) 				evid <= #1 0;
  else if (curr_state == RESET)  	evid <= #1 0;
  else if (curr_state == PRESET) 	evid <= #1 preset;
  else if (curr_state == INCREMENT) 	evid <= #1 evid+1;
end

always @(posedge clk25) begin

    if (reset) curr_state <= #1 RESET;
    
    else if (curr_state == RESET) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (preset_pulse) 		curr_state <= #1 PRESET;
      else if (trigger) 		curr_state <= #1 INCREMENT;
      else 				curr_state <= #1 WAITING;
    end
    
    else if (curr_state == PRESET) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (trigger) 		curr_state <= #1 INCREMENT;
      else 				curr_state <= #1 WAITING;
    end

    else if (curr_state == WAITING) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (preset_pulse) 		curr_state <= #1 PRESET;
      else if (trigger) 		curr_state <= #1 INCREMENT;
      else 				curr_state <= #1 WAITING;
    end

    else if (curr_state == INCREMENT) begin
      if (global_reset_pulse) 		curr_state <= #1 RESET;
      else if (preset_pulse) 		curr_state <= #1 PRESET;
      else 				curr_state <= #1 WAITING;
    end

end

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


`timescale 1ns/100ps

module l1_trig_pipe(clk25, reset, trig_in,
                    pipe_length, trig_out);

input clk25, reset, trig_in;
input [6:0] pipe_length;
output trig_out;

delay_64_stage del64(clk25, reset, pipe_length[6], trig_in, del64_out);
delay_32_stage del32(clk25, reset, pipe_length[5], del64_out, del32_out);
delay_16_stage del16(clk25, reset, pipe_length[4], del32_out, del16_out);
delay_8_stage del8(clk25, reset, pipe_length[3], del16_out, del8_out);
delay_4_stage del4(clk25, reset, pipe_length[2], del8_out, del4_out);
delay_2_stage del2(clk25, reset, pipe_length[1], del4_out, del2_out);
delay_1_stage del1(clk25, reset, pipe_length[0], del2_out, trig_out);


endmodule


module ff_clr(clk, reset, d, q);

input clk, reset, d;
output q;
reg q;

always @(posedge clk) begin
    if (reset) q <= #1 0;
    else q <= #1 d;
end

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_1_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q);

assign #1 out = delay ? ff0_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_2_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q);

assign #1 out = delay ? ff1_q : in;


// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_4_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q),
       ff2(clk, reset, ff1_q, ff2_q),
       ff3(clk, reset, ff2_q, ff3_q);
  
assign #1 out = delay ? ff3_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_8_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q),
       ff2(clk, reset, ff1_q, ff2_q),
       ff3(clk, reset, ff2_q, ff3_q),
       ff4(clk, reset, ff3_q, ff4_q),
       ff5(clk, reset, ff4_q, ff5_q),
       ff6(clk, reset, ff5_q, ff6_q),
       ff7(clk, reset, ff6_q, ff7_q);
              
assign #1 out = delay ? ff7_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_16_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q),
       ff2(clk, reset, ff1_q, ff2_q),
       ff3(clk, reset, ff2_q, ff3_q),
       ff4(clk, reset, ff3_q, ff4_q),
       ff5(clk, reset, ff4_q, ff5_q),
       ff6(clk, reset, ff5_q, ff6_q),
       ff7(clk, reset, ff6_q, ff7_q),
       ff8(clk, reset, ff7_q, ff8_q),
       ff9(clk, reset, ff8_q, ff9_q),
       ff10(clk, reset, ff9_q, ff10_q),
       ff11(clk, reset, ff10_q, ff11_q),
       ff12(clk, reset, ff11_q, ff12_q),
       ff13(clk, reset, ff12_q, ff13_q),
       ff14(clk, reset, ff13_q, ff14_q),
       ff15(clk, reset, ff14_q, ff15_q);
              
assign #1 out = delay ? ff15_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_32_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q),
       ff2(clk, reset, ff1_q, ff2_q),
       ff3(clk, reset, ff2_q, ff3_q),
       ff4(clk, reset, ff3_q, ff4_q),
       ff5(clk, reset, ff4_q, ff5_q),
       ff6(clk, reset, ff5_q, ff6_q),
       ff7(clk, reset, ff6_q, ff7_q),
       ff8(clk, reset, ff7_q, ff8_q),
       ff9(clk, reset, ff8_q, ff9_q),
       ff10(clk, reset, ff9_q, ff10_q),
       ff11(clk, reset, ff10_q, ff11_q),
       ff12(clk, reset, ff11_q, ff12_q),
       ff13(clk, reset, ff12_q, ff13_q),
       ff14(clk, reset, ff13_q, ff14_q),
       ff15(clk, reset, ff14_q, ff15_q),
       ff16(clk, reset, ff15_q, ff16_q),
       ff17(clk, reset, ff16_q, ff17_q),
       ff18(clk, reset, ff17_q, ff18_q),
       ff19(clk, reset, ff18_q, ff19_q),
       ff20(clk, reset, ff19_q, ff20_q),
       ff21(clk, reset, ff20_q, ff21_q),
       ff22(clk, reset, ff21_q, ff22_q),
       ff23(clk, reset, ff22_q, ff23_q),
       ff24(clk, reset, ff23_q, ff24_q),
       ff25(clk, reset, ff24_q, ff25_q),
       ff26(clk, reset, ff25_q, ff26_q),
       ff27(clk, reset, ff26_q, ff27_q),
       ff28(clk, reset, ff27_q, ff28_q),
       ff29(clk, reset, ff28_q, ff29_q),
       ff30(clk, reset, ff29_q, ff30_q),
       ff31(clk, reset, ff30_q, ff31_q);
              
assign #1 out = delay ? ff31_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule


module delay_64_stage(clk, reset, delay, in, out);

input clk, reset, in, delay;
output out;

ff_clr ff0(clk, reset, in, ff0_q),
       ff1(clk, reset, ff0_q, ff1_q),
       ff2(clk, reset, ff1_q, ff2_q),
       ff3(clk, reset, ff2_q, ff3_q),
       ff4(clk, reset, ff3_q, ff4_q),
       ff5(clk, reset, ff4_q, ff5_q),
       ff6(clk, reset, ff5_q, ff6_q),
       ff7(clk, reset, ff6_q, ff7_q),
       ff8(clk, reset, ff7_q, ff8_q),
       ff9(clk, reset, ff8_q, ff9_q),
       ff10(clk, reset, ff9_q, ff10_q),
       ff11(clk, reset, ff10_q, ff11_q),
       ff12(clk, reset, ff11_q, ff12_q),
       ff13(clk, reset, ff12_q, ff13_q),
       ff14(clk, reset, ff13_q, ff14_q),
       ff15(clk, reset, ff14_q, ff15_q),
       ff16(clk, reset, ff15_q, ff16_q),
       ff17(clk, reset, ff16_q, ff17_q),
       ff18(clk, reset, ff17_q, ff18_q),
       ff19(clk, reset, ff18_q, ff19_q),
       ff20(clk, reset, ff19_q, ff20_q),
       ff21(clk, reset, ff20_q, ff21_q),
       ff22(clk, reset, ff21_q, ff22_q),
       ff23(clk, reset, ff22_q, ff23_q),
       ff24(clk, reset, ff23_q, ff24_q),
       ff25(clk, reset, ff24_q, ff25_q),
       ff26(clk, reset, ff25_q, ff26_q),
       ff27(clk, reset, ff26_q, ff27_q),
       ff28(clk, reset, ff27_q, ff28_q),
       ff29(clk, reset, ff28_q, ff29_q),
       ff30(clk, reset, ff29_q, ff30_q),
       ff31(clk, reset, ff30_q, ff31_q),
       ff32(clk, reset, ff31_q, ff32_q),
       ff33(clk, reset, ff32_q, ff33_q),
       ff34(clk, reset, ff33_q, ff34_q),
       ff35(clk, reset, ff34_q, ff35_q),
       ff36(clk, reset, ff35_q, ff36_q),
       ff37(clk, reset, ff36_q, ff37_q),
       ff38(clk, reset, ff37_q, ff38_q),
       ff39(clk, reset, ff38_q, ff39_q),
       ff40(clk, reset, ff39_q, ff40_q),
       ff41(clk, reset, ff40_q, ff41_q),
       ff42(clk, reset, ff41_q, ff42_q),
       ff43(clk, reset, ff42_q, ff43_q),
       ff44(clk, reset, ff43_q, ff44_q),
       ff45(clk, reset, ff44_q, ff45_q),
       ff46(clk, reset, ff45_q, ff46_q),
       ff47(clk, reset, ff46_q, ff47_q),
       ff48(clk, reset, ff47_q, ff48_q),
       ff49(clk, reset, ff48_q, ff49_q),
       ff50(clk, reset, ff49_q, ff50_q),
       ff51(clk, reset, ff50_q, ff51_q),
       ff52(clk, reset, ff51_q, ff52_q),
       ff53(clk, reset, ff52_q, ff53_q),
       ff54(clk, reset, ff53_q, ff54_q),
       ff55(clk, reset, ff54_q, ff55_q),
       ff56(clk, reset, ff55_q, ff56_q),
       ff57(clk, reset, ff56_q, ff57_q),
       ff58(clk, reset, ff57_q, ff58_q),
       ff59(clk, reset, ff58_q, ff59_q),
       ff60(clk, reset, ff59_q, ff60_q),
       ff61(clk, reset, ff60_q, ff61_q),
       ff62(clk, reset, ff61_q, ff62_q),
       ff63(clk, reset, ff62_q, ff63_q);
              
assign #1 out = delay ? ff63_q : in;

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule






`timescale 1ns/100ps

module tdc_comm_fsm(clk25, reset, trigger, bc_reset, ec_reset,
                    global_reset, tdc_command_data, busy);

input clk25, reset, trigger, bc_reset, ec_reset, global_reset;
output tdc_command_data, busy;

reg tdc_command_data, busy;

reg [14:0] curr_state;


parameter       WAITING  =     15'b000000000000000, 
                TRG_BIT1 =     15'b000000000000010,
                TRG_BIT2 =     15'b000000000000100,
                TRG_BIT3 =     15'b000000000001000,
                BCR_BIT1 =     15'b000000000010000,
                BCR_BIT2 =     15'b000000000100000,
                BCR_BIT3 =     15'b000000001000000,
                ECR_BIT1 =     15'b000000010000000,
                ECR_BIT2 =     15'b000000100000000,
                ECR_BIT3 =     15'b000001000000000,
                GLR_BIT1 =     15'b000010000000000,
                GLR_BIT2 =     15'b000100000000000,
                GLR_BIT3 =     15'b001000000000000,
		TRG_BIT4 =     15'b010000000000000,
		TRG_BIT5 =     15'b100000000000000;

always @(posedge clk25) begin

    if (reset == 1) curr_state <= #1 WAITING;
    
    else if (curr_state == WAITING) begin
      tdc_command_data <= #1 0;
      busy <= #1 0;

      if (trigger)           curr_state <= #1 TRG_BIT1;
      else if (bc_reset)     curr_state <= #1 BCR_BIT1;
      else if (ec_reset)     curr_state <= #1 ECR_BIT1;
      else if (global_reset) curr_state <= #1 GLR_BIT1;
      else                   curr_state <= #1 WAITING;
    end
    
    else if (curr_state == TRG_BIT1) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 TRG_BIT2;
    end

    else if (curr_state == TRG_BIT2) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 TRG_BIT3;
    end

    else if (curr_state == TRG_BIT3) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 TRG_BIT4;
    end

    else if (curr_state == TRG_BIT4) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 TRG_BIT5;
    end

    else if (curr_state == TRG_BIT5) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 WAITING;
    end

    else if (curr_state == BCR_BIT1) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 BCR_BIT2;
    end

    else if (curr_state == BCR_BIT2) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 BCR_BIT3;
    end

    else if (curr_state == BCR_BIT3) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 WAITING;
    end

    else if (curr_state == ECR_BIT1) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 ECR_BIT2;
    end

    else if (curr_state == ECR_BIT2) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 ECR_BIT3;
    end

    else if (curr_state == ECR_BIT3) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 WAITING;
    end

    else if (curr_state == GLR_BIT1) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 GLR_BIT2;
    end

    else if (curr_state == GLR_BIT2) begin
      tdc_command_data <= #1 0;
      busy <= #1 1;

      curr_state <= #1 GLR_BIT3;
    end

    else if (curr_state == GLR_BIT3) begin
      tdc_command_data <= #1 1;
      busy <= #1 1;

      curr_state <= #1 WAITING;
    end

end

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule



`timescale 1ns/100ps

module trigger_mask_fsm(clk25, reset, trigger, busy);

input clk25, reset, trigger;
output busy;

reg busy;

reg [5:0] curr_state;

parameter       WAITING  =      6'b000000, 
                TRG1     =      6'b000010,
                TRG2     =      6'b000100,
                TRG3     =      6'b001000,
                TRG4     =      6'b010000,
                TRG5     =      6'b100000;

always @(posedge clk25) begin

    if (reset) curr_state <= #1 WAITING;
    
    else if (curr_state == WAITING) begin
      busy <= #1 0;

      if (trigger) curr_state <= #1 TRG1;
      else         curr_state <= #1 WAITING;
    end

    else if (curr_state == TRG1) begin
      busy <= #1 1;

      curr_state <= #1 TRG2;
    end

    else if (curr_state == TRG2) begin
      busy <= #1 1;

      curr_state <= #1 TRG3;
    end

    else if (curr_state == TRG3) begin
      busy <= #1 1;

      curr_state <= #1 TRG4;
    end

    else if (curr_state == TRG4) begin
      busy <= #1 1;

      curr_state <= #1 TRG5;
    end

    else if (curr_state == TRG5) begin
      busy <= #1 1;

      curr_state <= #1 WAITING;
    end

end

// STARTUP u0 (.GSR(reset), .GTS(1'b0), .CLK(1'b0));

endmodule